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| Features * 8-bit Microcontroller Compatible with MCS(R)51 Products * Enhanced 8051 Architecture - Single Clock Cycle per Byte Fetch - Up to 20 MIPS Throughput at 20 MHz Clock Frequency - Fully Static Operation: 0 Hz to 20 MHz - On-chip 2-cycle Hardware Multiplier - 128 x 8 Internal RAM - 4-level Interrupt Priority Nonvolatile Program Memory - 2K Bytes of In-System Programmable (ISP) Flash Memory - Endurance: Minimum 10,000 Write/Erase Cycles - Data Retention: Minimum 10 Years - Serial Interface for Program Downloading - 32-byte Fast Page Programming Mode - 64-byte User Signature Array - 2-level Program Memory Lock for Software Security Peripheral Features - Two 16-bit Enhanced Timer/Counters - Two 8-bit PWM Outputs (AT89LP213 only) - Enhanced UART with Automatic Address Recognition and Framing Error Detection (AT89LP214 only) - Enhanced Master/Slave SPI with Double-buffered Send/Receive - Programmable Watchdog Timer with Software Reset - Analog Comparator with Selectable Interrupt and Debouncing - 8 General-purpose Interrupt Pins Special Microcontroller Features - Two-wire On-chip Debug Interface - Brown-out Detection and Power-on Reset with Power-off Flag - Internal RC Oscillator - Low Power Idle and Power-down Modes - Interrupt Recovery from Power-down Mode I/O and Packages - Up to 12 Programmable I/O Lines - Configurable I/O with Quasi-bidirectional, Input, Push-pull Output, and Open-drain Modes - 5V Tolerant I/O - 14-lead TSSOP or PDIP Operating Conditions - 2.4V to 5.5V VCC Voltage Range - -40 C to 85C Temperature Range * * 8-bit Microcontroller with 2K Bytes Flash AT89LP213 AT89LP214 Preliminary * * * 1. Description The AT89LP213/214 is a low-power, high-performance CMOS 8-bit microcontroller with 2K bytes of In-System Programmable Flash memory. The device is manufactured using Atmel's high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. The AT89LP213/214 is built around an enhanced CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instructions to execute in 12, 24 or 48 clock cycles. In the AT89LP213/214 CPU, instructions need only 1 to 4 clock cycles providing 6 to 12 times more throughput than the standard 8051. Seventy percent of instructions need only as many clock cycles as they 3538A-MICRO-7/06 have bytes to execute, and most of the remaining instructions require only one additional clock. The enhanced CPU core is capable of 20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same current consumption. Conversely, at the same throughput as the classic 8051, the new CPU core runs at a much lower speed and thereby greatly reduces power consumption. The AT89LP213/214 provides the following standard features: 2K bytes of In-System Programmable Flash memory, 128 bytes of RAM, up to 12 I/O lines, two 16-bit timer/counters, two PWM outputs (AT89LP213 only), a programmable watchdog timer, a full duplex serial port (AT89LP214 only), a serial peripheral interface, an internal RC oscillator, on-chip crystal oscillator, and a four-level, six-vector interrupt system. The two timer/counters in the AT89LP213/214 are enhanced with two new modes. Mode 0 can be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit auto-reload timer/counter. In addition, the timer/counters on the AT89LP213 may independently drive a pulse width modulation output. The I/O ports of the AT89LP213/214 can be independently configured in one of four operating modes. In quasi-bidirectional mode, the ports operate as in the classic 8051. In input mode, the ports are tristated. Push-pull output mode provides full CMOS drivers and open-drain mode provides just a pull-down. In addition, all 8 pins of Port 1 can be configured to generate an interrupt using the general-purpose interrupt interface. The I/O pins of the AT89LP213/214 tolerate voltages higher than the device's own power supply, up to 5.5V. When the device is supplied at 2.4V and all I/O ports receive 5.5V, the total back flowing current an all I/Os is less than 100 A. 2. Pin Configuration 2.1 AT89LP213: 14-lead TSSOP/PDIP (GPI5/MOSI) P1.5 (GPI7/SCK) P1.7 (GPI5/RST) P1.3 GND (GPI2) P1.2 (T0) P3.4 (INT0/XTAL1) P3.2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 P1.6 (MISO/GPI6) P1.4 (SS/GPI4) P1.1 (AIN1/GPI1) P1.0 (AIN0/GPI0) VCC P3.5 (T1) P3.3 (XTAL2/CLKOUT/INT1) 2.2 AT89LP214: 14-lead TSSOP/PDIP (GPI5/MOSI) P1.5 (GPI7/SCK) P1.7 (GPI5/RST) P1.3 GND (GPI2) P1.2 (RxD) P3.0 (INT0/XTAL1) P3.2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 P1.6 (MISO/GPI6) P1.4 (SS/GPI4) P1.1 (AIN1/GPI1) P1.0 (AIN0/GPI0) VCC P3.1 (TxD) P3.3 (XTAL2/CLKOUT/INT1) 2 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 3. Pin Description Table 3-1. Pin AT89LP213 Pin Description Type I/O I/O I I/O I/O I I/O I I I I I/O I I/O I/O I/O I Description P1.5: User-configurable I/O Port 1 bit 5. MOSI: SPI master-out/slave-in. When configured as master, this pin is an output. When configured as slave, this pin is an input. GPI5: General-purpose Interrupt input 5. P1.7: User-configurable I/O Port 1 bit 7. SCK: SPI Clock. When configured as master, this pin is an output. When configured as slave, this pin is an input. GPI7: General-purpose Interrupt input 7. P1.3: User-configurable I/O Port 1 bit 3 (if Reset Fuse is disabled). RST: External Active-Low Reset input (if Reset Fuse is enabled. See "External Reset" on page 15). GPI3: General-purpose Interrupt input 3. DCL: Serial Clock input for On-chip Debug Interface when OCD is enabled. Ground P1.2: User-configurable I/O Port 1 bit 2. GPI2: General-purpose Interrupt input 2. P3.4: User-configurable I/O Port 3 bit 4. T0: Timer/Counter 0 External Input or PWM Output. P3.2: User-configurable I/O Port 3 bit 2. XTAL1: Input to the inverting oscillator amplifier and internal clock generation circuits. It may be used as a port pin if the internal RC oscillator is selected as the clock source. DDA: Serial Data input/output for On-chip Debug Interface when OCD is enabled and the internal RC oscillator is selected as the clock source. P3.3: User-configurable I/O Port 3 bit 3. XTAL2: Output from inverting oscillator amplifier. It may be used as a port pin if the internal RC oscillator is selected as the clock source. CLKOUT: When the internal RC oscillator is selected as the clock source, may be used to output the internal clock divided by 2. DDA: Serial Data input/output for On-chip Debug Interface when OCD is enabled and the external clock is selected as the clock source. P3.5: User-configurable I/O Port 3 bit 5. T1: Timer/Counter 1 External input or PWM output. Supply Voltage P1.0: User-configurable I/O Port 1 bit 0. AIN0: Analog Comparator Positive input. GPI0: General-purpose Interrupt input 0. P1.1: User-configurable I/O Port 1 bit 1. AIN1: Analog Comparator Negative input. GPI1: General-purpose Interrupt input 1 P1.4: User-configurable I/O Port 1 bit 4. SS: SPI slave select input. GPI4: General-purpose Interrupt input 4. P1.6: User-configurable I/O Port 1 bit 6. MISO: SPI master-in/slave-out. When configured as master, this pin is an input. When configured as slave, this pin is an output. GPI6: General-purpose Interrupt input 6. Symbol 1 P1.5 2 P1.7 3 P1.3 4 5 6 GND P1.2 P3.4 7 P3.2 I/O I/O O 8 P3.3 O I/O I/O I/O I I/O I I I/O I I I/O I I I/O I/O I 9 10 11 P3.5 VDD P1.0 12 P1.1 13 P1.4 14 P1.6 3 3538A-MICRO-7/06 Table 3-2. Pin AT89LP214 Pin Description Type I/O I/O I I/O I/O I I/O I I I I I/O I I/O I I/O I Description P1.5: User-configurable I/O Port 1 bit 5. MOSI: SPI master-out/slave-in. When configured as master, this pin is an output. When configured as slave, this pin is an input. GPI5: General-purpose Interrupt input 5. P1.7: User-configurable I/O Port 1 bit 7. SCK: SPI Clock. When configured as master, this pin is an output. When configured as slave, this pin is an input. GPI7: General-purpose Interrupt input 7. P1.3: User-configurable I/O Port 1 bit 3 (if Reset Fuse is disabled). RST: External Active-Low Reset input (if Reset Fuse is enabled. See "External Reset" on page 15). GPI3: General-purpose Interrupt input 3. DCL: Serial Clock input for On-chip Debug Interface. Ground P1.2: User-configurable I/O Port 1 bit 2. GPI2: General-purpose Interrupt input 2. P3.0: User-configurable I/O Port 3 bit 0. RXD: Serial Port Receiver input. P3.2: User-configurable I/O Port 3 bit 2. XTAL1: Input to the inverting oscillator amplifier and internal clock generation circuits. It may be used as a port pin if the internal RC oscillator is selected as the clock source. DDA: Serial Data input/output for On-chip Debug Interface when OCD is enabled and the internal RC oscillator is selected as the clock source. P3.3: User-configurable I/O Port 3 bit 3. XTAL2: Output from inverting oscillator amplifier. It may be used as a port pin if the internal RC oscillator is selected as the clock source. CLKOUT: When the internal RC oscillator is selected as the clock source, may be used to output the internal clock divided by 2. DDA: Serial Data input/output for On-chip Debug Interface when OCD is enabled and the external clock is selected as the clock source.\ P3.1: User-configurable I/O Port 3 bit 1. TXD: Serial Port Transmitter output. Supply Voltage P1.0: User-configurable I/O Port 1 bit 0. AIN0: Analog Comparator Positive input. GPI0: General-purpose Interrupt input 0. P1.1: User-configurable I/O Port 1 bit 1. AIN1: Analog Comparator Negative input. GPI1: General-purpose Interrupt input 1 P1.4: User-configurable I/O Port 1 bit 4. SS: SPI slave select input. GPI4: General-purpose Interrupt input 4. P1.6: User-configurable I/O Port 1 bit 6. MISO: SPI master-in/slave-out. When configured as master, this pin is an input. When configured as slave, this pin is an output. GPI6: General-purpose Interrupt input 6. Symbol 1 P1.5 2 P1.7 3 P1.3 4 5 6 GND P1.2 P3.0 7 P3.2 I/O I/O O 8 P3.3 O I/O I/O O I I/O I I I/O I I I/O I I I/O I/O I 9 10 11 P3.1 VDD P1.0 12 P1.1 13 P1.4 14 P1.6 4 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 4. Block Diagram Figure 4-1. AT89LP213 Block Diagram Single Cycle 8051 CPU SPI 2KB Flash Timer 0 Timer 1 128 Bytes RAM Analog Comparator Port 3 Configurable I/O Watchdog Timer Port 1 Configurable I/O On-Chip RC Oscillator General-purpose Interrupt CPU Clock Configurable Oscillator Crystal or Resonator Figure 4-2. AT89LP214 Block Diagram Single Cycle 8051 CPU UART 2KB Flash SPI 128 Bytes RAM Timer 0 Timer 1 Port 3 Configurable I/O Analog Comparator Port 1 Configurable I/O Watchdog Timer General-purpose Interrupt On-Chip RC Oscillator CPU Clock Configurable Oscillator Crystal or Resonator 5 3538A-MICRO-7/06 5. Comparison to Standard 8051 The AT89LP213/214 is part of a family of devices with enhanced features that are fully binary compatible with the MCS-51 instruction set. In addition, most SFR addresses, bit assignments, and pin alternate functions are identical to Atmel's existing standard 8051 products. However, due to the high performance nature of the device, some system behaviors are different from those of Atmel's standard 8051 products such as AT89S52 or AT89S2051. The differences from the standard 8051 are outlined in the following paragraphs. 5.1 System Clock The CPU clock frequency equals the external XTAL1 frequency. The oscillator is no longer divided by 2 to provide the internal clock, and x2 mode is not supported. 5.2 Instruction Execution with Single-cycle Fetch The CPU fetches one code byte from memory every clock cycle instead of every six clock cycles. This greatly increases the throughput of the CPU. As a consequence, the CPU no longer executes instructions in 12 to 48 clock cycles. Each instruction executes in only 1 to 4 clock cycles. See "Instruction Set Summary" on page 59 for more details. 5.3 Interrupt Handling The interrupt controller polls the interrupt flags during the last clock cycle of any instruction. In order for an interrupt to be serviced at the end of an instruction, its flag needs to have been latched as active during the next to last clock cycle of the instruction, or in the last clock cycle of the previous instruction if the current instruction executes in only a single clock cycle. The external interrupt pins, INT0 and INT1, are sampled at every clock cycle instead of once every 12 clock cycles. Coupled with the shorter instruction timing and faster interrupt response, this leads to a higher maximum rate of incidence for the external interrupts. 5.4 Timer/Counters By default the Timer/Counters is incremented at a rate of once per clock cycle. This compares to once every 12 clocks in the standard 8051. A common prescaler is available to divide the time base for all timers and reduce the increment rate. The TPS bits in the CLKREG SFR control the prescaler (Table 9-2 on page 13). Setting TPS = 1011B will cause the timers to count once every 12 clocks. The external Timer/Counter pins, T0 and T1, are sampled at every clock cycle instead of once every 12 clock cycles. This increases the maximum rate at which the Counter modules may function. 5.5 Serial Port The baud rate of the UART in Mode 0 is 1/2 the clock frequency, compared to 1/12 the clock frequency in the standard 8051; and output data is only stable around the rising edge of the serial clock. In should also be noted that when using Timer 1 to generate the baud rate in Mode 1 or Mode 3, the timer counts at the clock frequency and not at 1/12 the clock frequency. To maintain the same baud rate in the AT89LP214 while running at the same frequency as a standard 8051, the time-out period must be 12 times longer. Mode 1 of Timer 1 supports 16-bit auto-reload to facilitate longer time-out periods for generating low baud rates. 6 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 5.6 Watchdog Timer The Watchdog Timer in AT89LP213/214 counts at a rate of once per clock cycle. This compares to once every 12 clocks in the standard 8051. A common prescaler is available to divide the time base for all timers and reduce the counting rate. 5.7 I/O Ports The I/O ports of the AT89LP213/214 may be configured in four different modes. By default all the I/O ports revert to input-only (tristated) mode at power-up or reset. In the standard 8051, all ports are weakly pulled high during power-up or reset. To enable 8051-like ports, the ports must be put into quasi-bidirectional mode by clearing the P1M0 and P3M0 SFRs. The user can also configure the ports to start in quasi-bidirectional mode by disabling the Tristate-Port User Fuse. When this fuse is disabled, P1M0 and P3M0 will reset to 00h instead of FFh and the ports will be weakly pulled high. 5.8 Reset The RST pin of the AT89LP213/214 is active-low as compared with the active high reset in the standard 8051. In addition, the RST pin is sampled every clock cycle and must be held low for a minimum of two clock cycles, instead of 24 clock cycles, to be recognized as a valid reset. 6. Memory Organization The AT89LP213/214 uses a Harvard Architecture with separate address spaces for program and data memory. The program memory has a regular linear address space with support for up to 64K bytes of directly addressable application code. The data memory has 128 bytes of internal RAM and 128 bytes of Special Function Register I/O space. The AT89LP213/214 does not support external data memory or external program memory. 6.1 Program Memory The AT89LP213/214 contains 2K bytes of on-chip In-System Programmable Flash memory for program storage. The Flash memory has an endurance of at least 10,000 write/erase cycles and a minimum data retention time of 10 years. The reset and interrupt vectors are located within the first 59 bytes of program memory (refer to Table 12-1 on page 19). Constant tables can be allocated within the entire 2K program memory address space for access by the MOVC instruction. The AT89LP213/214 does not support external program memory. Figure 6-1. Program Memory Map 007F User Signature Array 0040 001F Atmel Signature Array 0000 07FF Program Memory 0000 7 3538A-MICRO-7/06 A map of the AT89LP213/214 program memory is shown in Figure 6-1. In addition to the 2K code space from 0000h to 07FFh, the AT89LP213/214 also supports a 64-byte User Signature Array and a 32-byte Atmel Signature Array that are accessible by the CPU in a read-only fashion. In order to read from the signature arrays, the SIGEN bit in AUXR1 must be set. While SIGEN is one, MOVC A,@A+DPTR will access the signature arrays. The User Signature Array is mapped to addresses 0040h to 007Fh and the Atmel Signature Array is mapped to addresses 0000h to 001Fh. SIGEN must be cleared before using MOVC to access the code memory. The Atmel Signature Array is initialized with the Device ID in the factory. The User Signature Array is available for user identification codes or constant parameter data. Data stored in the signature array is not secure. Security bits will disable writes to the array; however, reads are always allowed. Table 6-1. AUXR1 - Auxiliary Register 1 Reset Value = XXXX 0XXXB AUXR1 = A2H Not Bit Addressable - Bit 7 - 6 - 5 - 4 SIGEN 3 - 2 - 1 - 0 6.2 Data Memory The AT89LP213/214 contains 128 bytes of general SRAM data memory plus 128 bytes of I/O memory mapped into a single 8-bit address space. The 128 bytes of data memory may be accessed through both direct and indirect addressing of the lower 128 byte addresses. The 128 bytes of I/O memory reside in the upper 128 byte address space (Figure 6-2). The I/O memory can only be accessed through direct addressing and contains the Special Function Registers (SFRs). Indirect accesses to the upper 128 byte addresses will return invalid data. The lowest 32 bytes of data memory are grouped into 4 banks of 8 registers each. The RS0 and RS1 bits (PSW.3 and PSW.4) select which register bank is in use. Instructions using register addressing will only access the currently specified bank. The AT89LP213/214 does not support external data memory. Figure 6-2. Data Memory Map FFH Accessible By Direct Addressing Only Special Function Registers Accessible By Direct and Indirect Addressing Only 0 8 UPPER 128 80H 7F H Ports Status and Control Bits Timers Registers Stack Pointer Accumulator (Etc.) LO WER 128 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 7. Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 7-1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write to these unlisted locations, since they may be used in future products to invoke new features. Table 7-1. AT89LP213/214 SFR Map and Reset Values 8 0F8H 0F0H 0E8H 0E0H 0D8H 0D0H 0C8H P1M0(2) IP x000 0000 P3 xx11 1111 IE 0000 0000 SADDR 0000 0000 AUXR1 xxxx 0xxx SCON 0000 0000 P1 1111 1111 TCON 0000 0000 SBUF xxxx xxxx TCONB 0010 0100 TMOD 0000 0000 SP 0000 0111 0 Notes: 1 GPMOD 0000 0000 RL0 0000 0000 TL0 0000 0000 DPL 0000 0000 2 GPLS 0000 0000 RL1 0000 0000 TL1 0000 0000 DPH 0000 0000 3 4 5 6 GPIEN 0000 0000 RH0 0000 0000 TH0 0000 0000 GPIF 0000 0000 RH1 0000 0000 TH1 0000 0000 ACSR xx00 0000 CLKREG 0000 x000 PCON 0000 0000 7 WDTRST (write-only) WDTCON 0000 x000 SADEN 0000 0000 IPH x000 0000 P1M1 xx00 0000 P3M0(2) P3M1 xx00 0000 PSW 0000 0000 B 0000 0000 SPSR 000x x000 ACC 0000 0000 SPCR 0000 0000 SPDR xxxx xxxx 9 A B C D E F 0FFH 0F7H 0EFH 0E7H 0DFH 0D7H 0CFH 0C7H 0BFH 0B7H 0AFH 0A7H 9FH 97H 8FH 87H 0C0H 0B8H 0B0H 0A8H 0A0H 98H 90H 88H 80H 1. All SFRs in the left-most column are bit-addressable. 2. Reset value is xx11 1111B when Tristate-Port Fuse is enabled and xx00 0000B when disabled. 9 3538A-MICRO-7/06 8. Enhanced CPU The AT89LP213/214 uses an enhanced 8051 CPU that runs at 6 to 12 times the speed of standard 8051 devices (or 3 to 6 times the speed of X2 8051 devices). The increase in performance is due to two factors. First, the CPU fetches one instruction byte from the code memory every clock cycle. Second, the CPU uses a simple two-stage pipeline to fetch and execute instructions in parallel. This basic pipelining concept allows the CPU to obtain up to 1 MIPS per MHz. A simple example is shown in Figure 8-1. The MCS-51 instruction set allows for instructions of variable length from 1 to 3 bytes. In a single-clock-per-byte-fetch system this means each instruction takes at least as many clocks as it has bytes to execute. The majority of instructions in the AT89LP213/214 follow this rule: the instruction execution time in clock cycles equals the number of bytes per instruction with a few exceptions. Branches and Calls require an additional cycle to compute the target address and some other complex instructions require multiple cycles. See "Instruction Set Summary" on page 59 for more detailed information on individual instructions. Figures 8-2 and 8-3 show examples of 1- and 2-byte instructions. Figure 8-1. Parallel Instruction Fetches and Executions Tn System Clock Tn+1 Tn+2 nth Instruction Fetch Execute (n+1)th Instruction Fetch Execute (n+2)th Instruction Fetch Figure 8-2. Single-cycle ALU Operation (Example: INC R0) T1 System Clock Total Execution Time Register Operand Fetch ALU Operation Execute Result Write Back Fetch Next Instruction T2 T3 10 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] Figure 8-3. Two-cycle ALU Operation (Example: ADD A, #data) T1 System Clock Total Execution Time Fetch Immediate Operand ALU Operation Execute Result Write Back Fetch Next Instruction T2 T3 8.1 Restrictions on Certain Instructions The AT89LP213/214 is an economical and cost-effective member of Atmel's growing family of microcontrollers. It contains 2K bytes of Flash program memory. It is fully compatible with the MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device. All the instructions related to jumping or branching should be restricted such that the destination address falls within the physical program memory space of the device, which is 2K for the AT89LP213/214. This should be the responsibility of the software programmer. For example, LJMP 7E0H would be a valid instruction, whereas LJMP 900H would not. 8.1.1 Branching Instructions The LCALL, LJMP, ACALL, AJMP, SJMP, and JMP @A+DPTR unconditional branching instructions will execute correctly as long as the programmer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size (locations 000H to 7FFH for the AT89LP213/214). Violating the physical space limits may cause unknown program behavior. With the CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, and JNZ conditional branching instructions, the same previous rule applies. Again, violating the memory boundaries may cause erratic execution. For applications involving interrupts the normal interrupt service routine address locations of the 8051 family architecture have been preserved. MOVX-related Instructions, Data Memory The AT89LP213/214 contains 128 bytes of internal data memory. RAM accesses to addresses above 7FH will return invalid data. Furthermore, the stack depth is limited to 128 bytes, the amount of available RAM. The Stack Pointer should not be allowed to point to locations above 7FH. External DATA memory access is not supported in this device, nor is external PROGRAM memory execution. Therefore, no MOVX [...] instructions should be included in the program. A typical 8051 assembler will still assemble instructions, even if they are written in violation of the restrictions mentioned above. It is the responsibility of the user to know the physical features and limitations of the device being used and to adjust the instructions used accordingly. 8.1.2 11 3538A-MICRO-7/06 9. System Clock The system clock is generated directly from one of three selectable clock sources. The three sources are the on-chip crystal oscillator, external clock source, and internal RC oscillator. The clock source is selected by the Clock Source User Fuses as shown in Table 9-1. No internal clock division is used to generate the CPU clock from the system clock. See "User Configuration Fuses" on page 71. Table 9-1. Clock Source Settings Clock Source Fuse 0 0 1 0 1 Selected Clock Source Crystal Oscillator Reserved External Clock on XTAL1 Internal 8 MHz RC Oscillator Clock Source Fuse 1 0 0 1 1 9.1 Crystal Oscillator When enabled, the internal inverting oscillator amplifier is connected between XTAL1 and XTAL2 for connection to an external quartz crystal or ceramic resonator. When using the crystal oscillator, P3.2 and P3.3 will have their inputs and outputs disabled. When using the crystal oscillator, XTAL2 should not be used to drive a board-level clock without a buffer. 9.2 External Clock Source The external clock option disables the oscillator amplifier and allows XTAL1 to be driven directly by the clock source. XTAL2 may be left unconnected, used as P3.3 I/O, or configured to output a divided version of the system clock. 9.3 Internal RC Oscillator The AT89LP213/214 has an internal RC oscillator tuned to 8.0 MHz 2.5%. When enabled as the clock source, XTAL1 and XTAL2 may be used as P3.2 and P3.3 respectively. XTAL2 may also be configured to output a divided version of the system clock. The frequency of the oscillator may be adjusted by changing the RC Adjust Fuses. (See "User Configuration Fuses" on page 71). 9.4 System Clock Out When the AT89LP213/214 is configured to use either an external clock or the internal RC oscillator, a divided version of the system clock may be output on XTAL2 (P3.3). The Clock Out feature is enabled by setting the COE bit in CLKREG. The two CDV bits determine the clock divide ratio. For example, setting COE = "1" and CDIV = "00" when using the internal oscillator will result in a 3.950 MHz (5%) clock output on P3.3. P3.3 must be configured as an output in order to use the clock out feature. 12 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] Table 9-2. CLKREG - Clock Control Register Reset Value = 0000 0000B CLKREG = 8FH Not Bit Addressable TPS3 Bit 7 TPS2 6 TPS1 5 TPS0 4 - 3 CDV1 2 CDV0 1 COE 0 Symbol TPS3 TPS2 TPS1 TPS0 Function Timer Prescaler. The Timer Prescaler selects the time base for Timer 0, Timer 1 and the Watchdog Timer. The prescaler is implemented as a 4-bit binary down counter. When the counter reaches zero it is reloaded with the value stored in the TPS bits to give a division ratio between 1 and 16. By default the timers will count every clock cycles (TPS = 0000B). To configure the timers to count at a standard 8051 rate of once every 12 clock cycles, TPS should be set to 1011B. Clock Out Division. Determines the frequency of the clock output relative to the system clock. CDIV1 CDIV0 0 1 0 1 Clock Out Frequency f/2 f/4 f/8 f/16 CDV1 CDV0 0 0 1 1 COE Clock Out Enable. Set COE to output a divided version of the system clock on XTAL2 (P3.3). The internal RC oscillator or external clock source must be selected in order to use this feature. 10. Reset During reset, all I/O Registers are set to their initial values, the port pins are tristated, and the program starts execution from the Reset Vector, 0000H. The AT89LP213/214 has five sources of reset: power-on reset, brown-out reset, external reset, watchdog reset, and software reset. 10.1 Power-on Reset A Power-on Reset (POR) is generated by an on-chip detection circuit. The detection level is nominally 1.4V. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the start-up reset or to detect a supply voltage failure in devices without a brown-out detector. The POR circuit ensures that the device is reset from power-on. A power-on sequence is shown in Figure 10-1 on page 14. When VCC reaches the Power-on Reset threshold voltage VPOR, an initialization sequence lasting tPOR is started. When the initialization sequence completes, the start-up timer determines how long the device is kept in POR after VCC rise. The POR signal is activated again, without any delay, when VCC falls below the POR threshold level. A Power-on Reset (i.e. a cold reset) will set the POF flag in PCON. The internally generated reset can be extended beyond the power-on period by holding the RST pin low longer than the time-out. 13 3538A-MICRO-7/06 Figure 10-1. Power-on Reset Sequence (BOD Disabled) VCC TIME-OUT VPOR tPOR + tSUT VPOR RST INTERNAL RESET RST INTERNAL RESET (RST Tied to VCC) (RST Controlled Externally) tRHD VRH If the Brown-out Detector (BOD) is also enabled, the start-up timer does not begin counting until after VCC reaches the BOD threshold voltage VBOD as shown in Figure 10-2. However, if this event occurs prior to the end of the initialization sequence, the timer must first wait for that sequence to complete before counting. Figure 10-2. Power-on Reset Sequence (BOD Enabled) VBOD VCC TIME-OUT VPOR tPOR tSUT RST INTERNAL RESET RST INTERNAL RESET (RST Tied to VCC) (RST Controlled Externally) VRH tRHD Note: tPOR is approximately 92 s 5%. The start-up timer delay is user configurable with the Start-up Time User Fuses and depends on the clock source (Table 10-1). The start-up delay should be selected to provide enough settling time for VCC and the selected clock source. The Start-Up Time fuses also control the length of the start-up time after a Brown-out Reset or when waking up from Power-down during internally timed mode. 14 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] Table 10-1. SUT Fuse 1 0 Start-up Timer Settings SUT Fuse 0 0 Crystal Oscillator Internal RC/External Clock 1024 s 512 s 2048 s 1024 s 4096 s 4096 s 16384 s Clock Source Internal RC/External Clock tSUT ( 5%) 16 s 0 1 Crystal Oscillator Internal RC/External Clock 1 0 Crystal Oscillator Internal RC/External Clock 1 1 Crystal Oscillator 10.2 Brown-out Reset The AT89LP213/214 has an on-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD is nominally 2.2V. The purpose of the BOD is to ensure that if VCC fails or dips while executing at speed, the system will gracefully enter reset without the possibility of errors induced by incorrect execution. A BOD sequence is shown in Figure 10-3. When VCC decreases to a value below the trigger level VBOD, the internal reset is immediately activated. When VCC increases above the trigger level, the start-up timer releases the internal reset after the specified time-out period has expired (Table 10-1). The Brown-out Detector must be enabled by setting the BOD Enable Fuse. (See "User Configuration Fuses" on page 71). Figure 10-3. Brown-out Detector Reset VCC TIME-OUT INTERNAL RESET VPOR VBOD tSUT 10.3 External Reset The P1.3/RST pin can function as either an active-LOW reset input or as a digital general purpose I/O, P1.3. The Reset Pin Enable Fuse, when set to "1", enables the external reset input function on P1.3. (See "User Configuration Fuses" on page 71). When cleared, P1.3 may be used as an input or output pin. When configured as a reset input, the pin must be held low for at least two clock cycles to trigger the internal reset. Note: During a power-up sequence, the fuse selection is always overridden and therefore the pin will always function as a reset input. An external circuit connected to this pin should not hold this pin LOW during a power-on sequence as this will keep the device in reset until the pin transitions high. After the power-up delay, this input will function either as an external reset input or as a digital input as defined by the fuse bit. Only a power-up reset will temporarily override the selection defined by the reset fuse bit. Other sources of reset will not override the reset fuse bit. P1.3/RST also serves as the In-System Programming (ISP) enable. ISP is enabled when the external reset pin is held low. When the reset pin is disabled by the fuse, ISP may only be entered by pulling P1.3 low during power-up. 15 3538A-MICRO-7/06 10.4 Watchdog Reset When the Watchdog times out, it will generate an internal reset pulse lasting 16 clock cycles. Watchdog reset will also set the WDTOVF flag in WDTCON. To prevent a Watchdog reset, the watchdog reset sequence 1EH/E1H must be written to WDTRST before the Watchdog times out. See "Programmable Watchdog Timer" on page 57 for details on the operation of the Watchdog. 10.5 Software Reset The CPU may generate an internal 16-clock cycle reset pulse by writing the software reset sequence 5AH/A5H to the WDRST register. A software reset will set the SWRST bit in WDTCON. See "Software Reset" on page 58 for more information on software reset. 11. Power Saving Modes The AT89LP213/214 supports two different power-reducing modes: Idle and Power-down. These modes are accessed through the PCON register. 11.1 Idle Mode Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU state is preserved in its entirety, including the RAM, stack pointer, program counter, program status word, and accumulator. The Port pins hold the logic states they had at the time that Idle was activated. Idle mode leaves the peripherals running in order to allow them to wake up the CPU when an interrupt is generated. The timers, UART, SPI, and GPI blocks continue to function during Idle. The comparator and watchdog may be selectively enabled or disabled during Idle. Any enabled interrupt source or reset may terminate Idle mode. When exiting Idle mode with an interrupt, the interrupt will immediately be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into Idle. 11.2 Power-down Mode Setting the Power-down (PD) bit in PCON enters Power-down mode. Power-down mode stops the oscillator and powers down the Flash memory in order to minimize power consumption. Only the power-on circuitry will continue to draw power during Power-down. During Power-down, the power supply voltage may be reduced to the RAM keep-alive voltage. The RAM contents will be retained, but the SFR contents are not guaranteed once VCC has been reduced. Power-down may be exited by external reset, power-on reset, or certain interrupts. 11.2.1 Interrupt Recovery from Power-down Three external interrupts may be configured to terminate Power-down mode. XTAL1 or XTAL2, when not used for the crystal oscillator or external clock, may be used to exit Power-down through external interrupts INT0 (P3.2) and INT1 (P3.3). To wake up by external interrupt INT0 or INT1, that interrupt must be enabled and configured for level-sensitive operation. General purpose interrupt 3 (GPI3) can also wake up the device when the RST pin is disabled. GPI3 must be enabled and configured for low level detection in order to terminate Power-down. When terminating Power-down by an interrupt, two different wake-up modes are available. When PWDEX in PCON is zero, the wake-up period is internally timed as shown in Figure 11-1. At the falling edge on the interrupt pin, Power-down is exited, the oscillator is restarted, and an internal timer begins counting. The internal clock will not be allowed to propagate to the CPU until after the timer has timed out. After the time-out period the interrupt service routine will 16 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] begin. The time-out period is controlled by the Start-up Timer Fuses (see Table 10-1 on page 15). The interrupt pin need not remain low for the entire time-out period. Figure 11-1. Interrupt Recovery from Power-down (PWDEX = 0) PWD XTAL1 tSUT INT1 INTERNAL CLOCK When PWDEX = "1", the wake-up period is controlled externally by the interrupt. Again, at the falling edge on the interrupt pin, power-down is exited and the oscillator is restarted. However, the internal clock will not propagate until the rising edge of the interrupt pin as shown in Figure 11-2. The interrupt pin should be held low long enough for the selected clock source to stabilize. After the rising edge on the pin the interrupt service routine will be executed. Figure 11-2. Interrupt Recovery from Power-down (PWDEX = 1) PWD XTAL1 INT1 INTERNAL CLOCK 11.2.2 Reset Recovery from Power-down The wake-up from Power-down through an external reset is similar to the interrupt with PWDEX = "0". At the falling edge of RST, Power-down is exited, the oscillator is restarted, and an internal timer begins counting as shown in Figure 11-3. The internal clock will not be allowed to propagate to the CPU until after the timer has timed out. The time-out period is controlled by the Start-up Timer Fuses. (See Table 10-1 on page 15). If RST returns high before the time-out, a two clock cycle internal reset is generated when the internal clock restarts. Otherwise the device will remain in reset until RST is brought high. 17 3538A-MICRO-7/06 Figure 11-3. Reset Recovery from Power-down. PWD XTAL1 tSUT RST INTERNAL CLOCK INTERNAL RESET Table 11-1. PCON - Power Control Register Reset Value = 000X 0000B PCON = 87H Not Bit Addressable SMOD1 Bit Symbol SMOD1 SMOD0 PWDEX POF GF1, GF0 PD IDL 7 Function Double Baud Rate bit. Doubles the baud rate of the UART in Modes 1, 2, or 3. SMOD0 6 PWDEX 5 POF 4 GF1 3 GF0 2 PD 1 IDL 0 Frame Error Select. When SMOD0 = 1, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after a frame error regardless of the state of SMOD0. Power-down Exit Mode. When PWDEX = 1, wake up from Power-down is externally controlled. When PWDEX = 1, wake up from Power-down is internally timed. Power Off Flag. POF is set to "1" during power up (i.e. cold reset). It can be set or reset under software control and is not affected by RST or BOD (i.e. warm resets). General-purpose Flags Power-down bit. Setting this bit activates power-down operation. Idle Mode bit. Setting this bit activates Idle mode operation 12. Interrupts The AT89LP213/214 provides 7 interrupt sources: two external interrupts, two timer interrupts, a serial port interrupt, a general-purpose interrupt, and an analog comparator interrupt. These interrupts and the system reset each have a separate program vector at the start of the program memory space. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable register IE. The IE register also contains a global disable bit, EA, which disables all interrupts. Each interrupt source (except the analog comparator) can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP and IPH. The analog comparator is fixed at the lowest priority level. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the end of an instruction, the request of higher priority level is serviced. If requests of the same priority level are pending at the end of an 18 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] instruction, an internal polling sequence determines which request is serviced. The polling sequence is based on the vector address; an interrupt with a lower vector address has higher priority than an interrupt with a higher vector address. Note that the polling sequence is only used to resolve pending requests of the same priority level. The External Interrupts INT0 and INT1 can each be either level-activated or edge-activated, depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these interrupts are the IE0 and IE1 bits in TCON. When the service routine is vectored to, hardware clears the flag that generated an external interrupt only if the interrupt was edge-activated. If the interrupt was level activated, then the external requesting source (rather than the on-chip hardware) controls the request flag. The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective Timer/Counter registers (except for Timer 0 in Mode 3). When a timer interrupt is generated, the on-chip hardware clears the flag that generated it when the service routine is vectored to. The Serial Port Interrupt is generated by the logic OR of RI and TI in SCON plus SPIF in SPSR. None of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine normally must determine whether RI, TI, or SPIF generated the interrupt, and the bit must be cleared by software. A logic OR of all eight flags in the GPIF register causes the general-purpose interrupt. None of these flags is cleared by hardware when the service routine is vectored to. The service routine must determine which bit generated the interrupt, and the bit must be cleared in software. If the interrupt was level activated, then the external requesting source must de-assert the interrupt before the flag may be cleared by software. The CF bit in ACSR generates the Comparator Interrupt. The flag is not cleared by hardware when the service routine is vectored to and must be cleared by software. Most of the bits that generate interrupts can be set or cleared by software, with the same result as though they had been set or cleared by hardware. That is, interrupts can be generated and pending interrupts can be canceled in software. The two exceptions are the SPI interrupt flag SPIF and the general-purpose interrupt flags in GPIF. These flags are only set by hardware and may only be cleared by software. Table 12-1. Interrupt System Reset Interrupt Vector Addresses Source RST or POR or BOD IE0 TF0 IE1 TF1 RI or TI or SPIF GPIF CF Vector Address 0000H 0003H 000BH 0013H 001BH 0023H 002BH 0033H External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Port General-purpose Interrupt Analog Comparator 19 3538A-MICRO-7/06 12.1 Interrupt Response Time The interrupt flags may be set by their hardware in any clock cycle. The interrupt controller polls the flags in the last clock cycle of the instruction in progress. If one of the flags was set in the preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine as the next instruction, provided that the interrupt is not blocked by any of the following conditions: an interrupt of equal or higher priority level is already in progress; the instruction in progress is RETI or any write to the IE, IP, or IPH registers. Either of these conditions will block the generation of the LCALL to the interrupt service routine. The second condition ensures that if the instruction in progress is RETI or any access to IE, IP or IPH, then at least one more instruction will be executed before any interrupt is vectored to. The polling cycle is repeated at the last cycle of each instruction, and the values polled are the values that were present at the previous clock cycle. If an active interrupt flag is not being serviced because of one of the above conditions and is no longer active when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle is new. If a request is active and conditions are met for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction executed. The call itself takes four cycles. Thus, a minimum of five complete clock cycles elapsed between activation of an interrupt request and the beginning of execution of the first instruction of the service routine. A longer response time results if the request is blocked by one of the previously listed conditions. If an interrupt of equal or higher priority level is already in progress, the additional wait time depends on the nature of the other interrupt's service routine. If the instruction in progress is not in its final clock cycle, the additional wait time cannot be more than 3 cycles, since the longest are only 4 cycles long. If the instruction in progress is RETI or an access to IE or IP, the additional wait time cannot be more than 7 cycles (a maximum of three more cycles to complete the instruction in progress, plus a maximum of 4 cycles to complete the next instruction). Thus, in a single-interrupt system, the response time is always more than 5 clock cycles and less than 13 clock cycles. See Figure 12-1 and Figure 12-2. Figure 12-1. Minimum Interrupt Response Time Clock Cycles INT0 IE0 Instruction Ack. 1 5 Cur. Instr. LCALL 1st ISR Instr. Figure 12-2. Maximum Interrupt Response Time Clock Cycles INT0 IE0 Instruction RETI Ack. 1 13 4 Cyc. Instr. LCALL 1st ISR In 20 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] Table 12-2. IE = A8H Bit Addressable EA Bit Symbol EA EC EGP ES ET1 EX1 ET0 EX0 . IE - Interrupt Enable Register Reset Value = 0000 0000B EC 6 EGP 5 ES 4 ET1 3 EX1 2 ET0 1 EX0 0 7 Function Global enable/disable. All interrupts are disabled when EA = 0. When EA = 1, each interrupt source is enabled/disabled by setting /clearing its own enable bit. Comparator Interrupt Enable General-purpose Interrupt Enable Serial Port Interrupt Enable Timer 1 Interrupt Enable External Interrupt 1 Enable Timer 0 Interrupt Enable External Interrupt 0 Enable IP - Interrupt Priority Register Reset Value = X000 0000B Table 12-3. IP = B8H Bit Addressable - Bit Symbol PGP PS PT1 PX1 PT0 PX0 7 Function - 6 PGP 5 PS 4 PT1 3 PX1 2 PT0 1 PX0 0 General-purpose Interrupt Priority Low Serial Port Interrupt Priority Low Timer 1 Interrupt Priority Low External Interrupt 1 Priority Low Timer 0 Interrupt Priority Low External Interrupt 0 Priority Low 21 3538A-MICRO-7/06 Table 12-4. IPH - Interrupt Priority High Register Reset Value = X000 0000B IPH = B7H Not Bit Addressable - Bit Symbol PGH PSH PT1H PX1H PT0H PX0H 7 Function - 6 PGH 5 PSH 4 PT1H 3 PX1H 2 PT0H 1 PX0H 0 General-purpose Interrupt Priority High Serial Port Interrupt Priority High Timer 1 Interrupt Priority High External Interrupt 1 Priority High Timer 0 Interrupt Priority High External Interrupt 0 Priority High 13. I/O Ports The AT89LP213/214 can be configured for between 9 and 12 I/O pins. The exact number of I/O pins available depends on the clock and reset options as shown in Table 13-1. All port pins are 5V tolerant, that is they can be pulled up or driven to 5.5V even when operating at a lower VCC such as 3V. Table 13-1. Clock Source External Crystal or Resonator No external reset External RST Pin External Clock No external reset External RST Pin Internal RC Oscillator No external reset 12 11 11 10 10 I/O Pin Configurations Reset Option External RST Pin Number of I/O Pins 9 13.1 Port Configuration All port pins on the AT89LP213/214 may be configured to one of four modes: quasi-bidirectional (standard 8051 port outputs), push-pull output, open-drain output, or input-only. Port modes may be assigned in software on a pin-by-pin basis as shown in Table 13-2. The Tristate-Port User Fuse determines the default state of the port pins. When the fuse is enabled, all port pins default to input-only mode after reset. When the fuse is disabled, all port pins, with the exception of P1.0 and P1.1, default to quasi-bidirectional mode after reset and are weakly pulled high. Each port pin also has a Schmitt-triggered input for improved input noise rejection. During Power-down all the Schmitt-triggered inputs are disabled with the exception of P1.3, P3.2 and P3.3, which may be used to wake up the device. Therefore P1.3, P3.2 and P3.3 should not be left floating during Power-down 22 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] . Table 13-2. PxM0.y 0 0 1 1 Configuration Modes for Port x, Bit y PxM1.y 0 1 0 1 Port Mode Quasi-bidirectional Push-pull Output Input Only (High Impedance) Open-drain Output 13.1.1 Quasi-bidirectional Output Port pins in quasi-bidirectional output mode function similar to standard 8051 port pins. A Quasibidirectional port can be used both as an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin is driven low, it is driven strongly and able to sink a large current. There are three pull-up transistors in the quasi-bidirectional output that serve different purposes. One of these pull-ups, called the "very weak" pull-up, is turned on whenever the port latch for the pin contains a logic "1". This very weak pull-up sources a very small current that will pull the pin high if it is left floating. A second pull-up, called the "weak" pull-up, is turned on when the port latch for the pin contains a logic "1" and the pin itself is also at a logic "1" level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a "1". If this pin is pulled low by an external device, this weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pull-up and pull the port pin below its input threshold voltage. The third pull-up is referred to as the "strong" pull-up. This pull-up is used to speed up low-tohigh transitions on a quasi-bidirectional port pin when the port latch changes from a logic "0" to a logic "1". When this occurs, the strong pull-up turns on for two CPU clocks quickly pulling the port pin high. The quasi-bidirectional port configuration is shown in Figure 13-1. The input circuitry of P1.3, P3.2 and P3.3 is not disabled during Power-down (see Figure 13-3). Figure 13-1. Quasi-bidirectional Output V CC V CC V CC 1 Clock Delay (D Flip-Flop) Strong Very Weak Weak Port Pin From Port Register Input Data PWD 23 3538A-MICRO-7/06 13.1.2 Input-only Mode The input only port configuration is shown in Figure 13-2. The output drivers are tristated. The input includes a Schmitt-triggered input for improved input noise rejection. The input circuitry of P1.3, P3.2 and P3.3 is not disabled during Power-down (see Figure 13-3). Input pins can be safely driven to 5.5V even when operating at lower VCC levels; however, the input threshold of the Schmitt trigger will be set by the VCC level and must be taken into consideration. Figure 13-2. Input Only Input Data PWD Figure 13-3. Input Only for P1.3, P3.2 and P3.3 Port Pin Input Data 13.1.3 Port Pin Open-drain Output The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port latch contains a logic "0". To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to VCC. The pulldown for this mode is the same as for the quasi-bidirectional mode. The open-drain port configuration is shown in Figure 13-4.The input circuitry of P1.3, P3.2 and P3.3 is not disabled during Power-down (see Figure 13-3). Open-drain pins can be safely pulled high to 5.5V even when operating at lower VCC levels; however, the input threshold of the Schmitt trigger will be set by the VCC level and must be taken into consideration. Figure 13-4. Open-drain Output Port Pin From Port Register Input Data PWD 13.1.4 Push-pull Output The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic "1". The push-pull mode may be used when more source current is needed from a port output. The push-pull port configuration is shown in Figure 13-5. The input circuitry of P1.3, P3.2 and P3.3 is not disabled during Power-down (see Figure 13-3). 24 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] Figure 13-5. Push-pull Output VCC Port Pin From Port Register Input Data PWD 13.2 Port 1 Analog Functions The AT89LP213/214 incorporates an analog comparator. In order to give the best analog performance and minimize power consumption, pins that are being used for analog functions must have both their digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port pins into the input-only mode as described in "Port Configuration" on page 22. Digital inputs on P1.0 and P1.1 are disabled whenever the Analog Comparator is enabled by setting the CEN bit in ACSR. CEN forces the PWD input on P1.0 and P1.1 low, thereby disabling the Schmitt trigger circuitry. P1.0 and P1.1 will always default to input-only mode after reset regardless of the state of the Tristate-Port Fuse. 13.3 Port Read-modify-write A read from a port will read either the state of the pins or the state of the port register depending on which instruction is used. Simple read instructions will always access the port pins directly. Read-modify-write instructions, which read a value, possibly modify it, and then write it back, will always access the port register. This includes bit write instructions such as CLR or SETB as they actually read the entire port, modify a single bit, then write the data back to the entire port. See Table 13-3 for a complete list of Read-modify-write instruction which may access the ports. Table 13-3. Mnemonic ANL ORL XRL JBC CPL INC DEC DJNZ MOV PX.Y, C CLR PX.Y SETB PX.Y Port Read-modify-write Instructions Instruction Logical AND Logical OR Logical EX-OR Jump if bit set and clear bit Complement bit Increment Decrement Decrement and jump if not zero Move carry to bit Y of Port X Clear bit Y of Port X Set bit Y of Port X Example ANL P1, A ORL P1, A XRL P1, A JBC P3.0, LABEL CPL P3.1 INC P1 DEC P3 DJNZ P3, LABEL MOV P1.0, C CLR P1.1 SETB P3.2 25 3538A-MICRO-7/06 13.4 Port Alternate Functions Most general-purpose digital I/O pins of the AT89LP213/214 share functionality with the various I/Os needed for the peripheral units. Table 13-5 lists the alternate functions of the port pins. Alternate functions are connected to the pins in a logic AND fashion. In order to enable the alternate function on a port pin, that pin must have a "1" in its corresponding port register bit, otherwise the input/output will always be "0". Furthermore, each pin must be configured for the correct input/output mode as required by its peripheral before it may be used as such. Table 13-4 shows how to configure a generic pin for use with an alternate function. Table 13-4. PxM0.y 0 0 1 1 Alternate Function Configurations for Pin y of Port x PxM1.y 0 1 0 1 Px.y 1 1 X 1 I/O Mode bidirectional (internal pull-up) output input bidirectional (external pull-up) Table 13-5. Port Pin Alternate Functions Configuration Bits Alternate Function AIN0 GPI0 AIN1 GPI1 GPI2 GPI3 SS GPI4 MOSI GPI5 MISO GPI6 SCK GPI7 RXD TXD INT0 INT1 CLKOUT T0 T1 CMPOUT AT89LP214 Only Internal RC Oscillator Only Internal RC Oscillator or External Clock Source Only AT89LP213 Only Pin is tied to comparator output RST must be disabled input-only Port Pin P1.0 PxM0.y P1M0.0 PxM1.y P1M1.0 Notes input-only P1.1 P1.2 P1.3 P1.4 P1M0.1 P1M0.2 P1M0.3 P1M0.4 P1M1.1 P1M1.2 P1M1.3 P1M1.4 P1.5 P1M0.5 P1M1.5 P1.6 P1M0.6 P1M1.6 P1.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P1M0.7 P3M0.0 P3M0.1 P3M0.2 P3M0.3 P3M0.4 P3M0.5 P1M1.7 P3M1.0 P3M1.1 P3M1.2 P3M1.3 P3M1.4 P3M1.5 not configurable 26 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 14. Enhanced Timer/Counters The AT89LP213/214 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1. As a Timer, the register increase every clock cycle by default. Thus, the register counts clock cycles. Since a clock cycle consists of one oscillator period, the count rate is equal to the oscillator frequency. The timer rate can be prescaled by a value between 1 and 16 using the Timer Prescaler (see Table 9-2 on page 13). Both Timers share the same prescaler. As a Counter, the register is incremented in response to a l-to-0 transition at its corresponding input pin, T0 or T1. The external input is sampled every clock cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during the cycle following the one in which the transition was detected. Since 2 clock cycles are required to recognize a l-to-0 transition, the maximum count rate is 1/2 of the oscillator frequency. There are no restrictions on the duty cycle of the input signal, but it should be held for at least one full clock cycle to ensure that a given level is sampled at least once before it changes. In the AT89LP214, the T0 and T1 inputs are not available at the pins. However, the inputs may be exercised in software by toggling the P3.4 and P3.5 bits in the Port 3 register. Furthermore, the Timer or Counter functions for Timer 0 and Timer 1 have four operating modes: variable width timer, 16-bit auto-reload timer, 8-bit auto-reload timer, and split timer. The control bits C/T in the Special Function Register TMOD select the Timer or Counter function. The bit pairs (M1, M0) in TMOD select the operating modes. 14.1 Mode 0 - Variable Width Timer/Counter Both Timers in Mode 0 are 8-bit Counters with a variable prescaler. The prescaler may vary from 1 to 8 bits depending on the PSC bits in TCONB, giving the timer a range of 9 to 16 bits. By default the timer is configured as a 13-bit timer compatible to Mode 0 in the standard 8051. Figure 14-1 shows the Mode 0 operation as it applies to Timer 1 in 13-bit mode. As the count rolls over from all "1"s to all "0"s, it sets the Timer interrupt flag TF1. The counter input is enabled to the Timer when TR1 = 1 and either GATE = 0 or INT1 = 1. Setting GATE = 1 allows the Timer to be controlled by external input INT1, to facilitate pulse width measurements. TR1 is a control bit in the Special Function Register TCON. GATE is in TMOD. The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should be ignored. Setting the run flag (TR1) does not clear the registers. Mode 0: 256 x 2 Time-out Period = ------------------------------------------------------ x ( TPS + 1 ) Oscillator Frequency PSC0 + 1 Note: RH1/RL1 are not required by Timer 1 during Mode 0 and may be used as temporary storage registers. 27 3538A-MICRO-7/06 Figure 14-1. Timer/Counter 1 Mode 0: Variable Width Counter OSC /TPS C/T = 0 TL1 (8 Bits) T1 Pin C/T = 1 Control PSC1 TR1 GATE TH1 (8 Bits) TF1 Interrupt INT1 Pin Mode 0 operation is the same for Timer 0 as for Timer 1, except that TR0, TF0 and INT0 replace the corresponding Timer 1 signals in Figure 14-1. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3). The INT0 and INT1 pins are shared with the XTAL oscillator. They may only be used for the GATE function when using the internal RC oscillator as the system clock. 14.2 Mode 1 - 16-bit Auto-Reload Timer/Counter In Mode 1 the Timers are configured for 16-bit auto-reload. The Timer register is run with all 16 bits. The 16-bit reload value is stored in the high and low reload registers (RH1/RL1). The clock is applied to the combined high and low timer registers (TH1/TL1). As clock pulses are received, the timer counts up: 0000H, 0001H, 0002H, etc. An overflow occurs on the FFFFH-to0000H transition, upon which the timer register is reloaded with the value from RH1/RL1 and the overflow flag bit in TCON is set. See Figure 14-2. The reload registers default to 0000H, which gives the full 16-bit timer period compatible with the standard 8051. Mode 1 operation is the same for Timer/Counter 0. Mode 1: ( 65536 - {RH0, RL0} ) Time-out Period = ---------------------------------------------------------- x ( TPS + 1 ) Oscillator Frequency Figure 14-2. Timer/Counter 1 Mode 1: 16-bit Auto-reload RL1 (8 Bits) OSC /TPS Reload RH1 (8 Bits) C/T = 0 TL1 (8 Bits) T1 Pin TH1 (8 Bits) TF1 Interrupt C/T =1 Control TR1 GATE INT1 Pin 28 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 14.3 Mode 2 - 8-bit Auto-reload Timer/Counter Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure 14-3. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged. Mode 2 operation is the same for Timer/Counter 0. Mode 2: ( 256 - TH0 ) Time-out Period = ------------------------------------------------------ x ( TPS + 1 ) Oscillator Frequency Figure 14-3. Timer/Counter 1 Mode 2: 8-bit Auto-reload OSC /TPS C/T = 0 TL1 (8 Bits) C/T = 1 TF1 Interrupt T1 Pin TR1 GATE Control Reload TH1 (8 Bits) INT0 Pin Note: RH1/RL1 are not required by Timer 1 during Mode 2 and may be used as temporary storage registers. 14.4 Mode 3 - 8-bit Split Timer Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in Figure 14-4. TL0 uses the Timer 0 control bits: C/T, GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the Timer 1 interrupt. While Timer 0 is in Mode 3, Timer 1 will still obey its settings in TMOD but cannot generate an interrupt. Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the AT89LP213/214 can appear to have three Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt. Figure 14-4. Timer/Counter 0 Mode 3: Two 8-bit Counters /TPS C/T = 0 C/T =1 T0 Pin Control (8 Bits) Interrupt GATE INT0 Pin /TPS Control (8 Bits) Interrupt Note: RH0/RL0 are not required by Timer 0 during Mode 3 and may be used as temporary storage registers. 29 3538A-MICRO-7/06 . Table 14-1. TCON - Timer/Counter Control Register Reset Value = 0000 0000B TCON = 88H Bit Addressable TF1 Bit Symbol TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 7 Function TR1 6 TF0 5 TR0 4 IE1 3 IT1 2 IE0 1 IT0 0 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to interrupt routine. Timer 1 run control bit. Set/cleared by software to turn Timer/Counter on/off. Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to interrupt routine. Timer 0 run control bit. Set/cleared by software to turn Timer/Counter on/off. Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. 30 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] Table 14-2. TMOD: Timer/Counter Mode Control Register Reset Value = 0000 0000B TMOD = 88H Not Bit Addressable GATE 7 C/T 6 Timer1 Gate Gating control when set. Timer/Counter x is enabled only while INTx pin is high and TRx control pin is set. When cleared, Timer x is enabled whenever TRx control bit is set. Timer or Counter Selector cleared for Timer operation (input from internal system clock). Set for Counter operation (input from Tx input pin). Timer 1 Mode bit 1 Timer 1 Mode bit 0 M1 5 M0 4 GATE 3 C/T 2 M1 1 Timer0 M0 0 Timer 0 gate bit C/T Timer 0 counter/timer select bit M1 M0 Timer 0 M1 bit Timer 0 M0 bit M1 0 0 1 M0 0 1 0 Mode 0 1 2 Operating Mode Variable 9 - 16-bit Timer mode. 8-bit Timer/Counter THx with TLx as 1 - 8-bit prescaler. 16-bit auto-reload mode. 16-bit Timer/Counters THx and TLx are cascaded; there is no prescaler. 8-bit auto reload. 8-bit auto-reload Timer/Counter THx holds a value which is to be reloaded into TLx each time it overflows. Split Timer mode. (Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits. (Timer 1) Timer/Counter 1 stopped. 1 1 3 1 1 3 Timer SFR TCON TMOD TL0 TL1 TH0 TH1 TCONB RL0 RL1 RH0 RH1 Purpose Control Mode Timer 0 low-byte Timer 1 low-byte Timer 0 high-byte Timer 1 high-byte Mode Timer 0 reload low-byte Timer 1 reload low-byte Timer 0 reload high-byte Timer 1 reload high-byte Address 88H 89H 8AH 8BH 8CH 8DH 91H 92H 93H 94H 95H Bit-Addressable Yes No No No No No No No No No No 31 3538A-MICRO-7/06 Table 14-3. . TCONB - Timer/Counter Control Register B Reset Value = 0010 0100B TCONB = 91H Not Bit Addressable PWM1EN Bit 7 PWM0EN 6 PSC12 5 PSC11 4 PSC10 3 PSC02 2 PSC01 1 PSC00 0 Symbol PWM1EN PWM0EN PSC12 PSC11 PSC10 PSC02 PSC01 PSC00 Function Configures Timer 1 for Pulse Width Modulation output on T1 (P3.5). Configures Timer 0 for Pulse Width Modulation output on T0 (P3.4). Prescaler for Timer 1 Mode 0. The number of active bits in TL1 equals PSC1 + 1. After reset PSC1 = 100B which enables 5 bits of TL1 for compatibility with the 13-bit Mode 0 in AT89S2051. Prescaler for Timer 0 Mode 0. The number of active bits in TL0 equals PSC0 + 1. After reset PSC0 = 100B which enables 5 bits of TL0 for compatibility with the 13-bit Mode 0 in AT89C52. 14.5 Pulse Width Modulation On the AT89LP213, Timer 0 and Timer 1 may be independently configured as 8-bit asymmetrical (edge-aligned) pulse width modulators (PWM) by setting the PWM0EN or PWM1EN bits in TCONB, respectively. In PWM Mode the generated waveform is output on the timer's input pin, T0 or T1. Therefore, C/T must be set to "0" when in PWM mode. and the T0 (P3.4) and T1 (P3.5) must be configured in an output mode. The Timer Overflow Flags and Interrupts will continue to function while in PWM Mode and Timer 1 may still generate the baud rate for the UART. Each PWM channel has four modes selected by the mode bits in TMOD. An example waveform for Timer 0 in PWM Mode 0 is shown in Figure 14-5. TH0 acts as an 8-bit counter while RH0 stores the 8-bit compare value. When TH0 is 00H the PWM output is set high. When the TH0 count reaches the value stored in RH0 the PWM output is set low. Therefore, the pulse width is proportional to the value in RH0. To prevent glitches, writes to RH0 only take effect on the FFH to 00H overflow of TH0. Setting RH0 to 00H will keep the PWM output low. Figure 14-5. Asymmetrical Pulse Width Modulation Counter Value (TH0) Compare Value (RH0) PWM Output (T0) 32 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 14.5.1 Mode 0 - 8-bit PWM with 8-bit Logarithmic Prescaler In Mode 0, TLx acts as a logarithmic prescaler driving 8-bit counter THx (see Figure 14-6). The PSCx bits in TCONB control the prescaler value. On THx overflow, the duty cycle value in RHx is transferred to OCRx and the output pin is set high. When the count in THx matches OCRx, the output pin is cleared low. The following formulas give the output frequency and duty cycle for Timer 0 in PWM Mode 0. Timer 1 in PWM Mode 0 is identical to Timer 0. Mode 0: Oscillator Frequency 1 f out = ------------------------------------------------------ x -------------------PSC0 + 1 TPS + 1 256 x 2 RH0 Duty Cycle % = 100 x ----------256 Mode 0: Figure 14-6. Timer/Counter 1 PWM Mode 0 RH1 (8 Bits) OSC /TPS Control TL1 (8 Bits) OCR1 = T1 PSC1 TR1 GATE TH1 (8 Bits) INT1 Pin 14.5.2 Mode 1 - 8-bit PWM with 8-bit Linear Prescaler In Mode 1, TLx provides linear prescaling with an 8-bit auto-reload from RLx (see Figure 14-7). On TLx overflow, TLx is loaded with the value of RLx. THx acts as an 8-bit counter. On THx overflow, the duty cycle value in RHx is transferred to OCRx and the output pin is set high. When the count in THx matches OCRx, the output pin is cleared low. The following formulas give the output frequency and duty cycle for Timer 0 in PWM Mode 1. Timer 1 in PWM Mode 1 is identical to Timer 0. Mode 1: Oscillator Frequency 1 f out = ------------------------------------------------------ x -------------------256 x ( 256 - RL0 ) TPS + 1 Mode 1: RH0 Duty Cycle % = 100 x ----------256 33 3538A-MICRO-7/06 Figure 14-7. Timer/Counter 1 PWM Mode 1 RH1 (8 Bits) RL1 (8 Bits) OCR1 = T1 OSC /TPS Control TL1 (8 Bits) TH1 (8 Bits) TR1 GATE INT1 Pin 14.5.3 Mode 2 - 8-bit Frequency Generator Timer 0 in PWM Mode 2 functions as an 8-bit auto-reload timer, the same as normal Mode 2, with the exception that the output pin T0 is toggled at every TL0 overflow (see Figure 14-8). Timer 1 in PWM Mode 2 is identical to Timer 0. PWM Mode 2 can be used to output a square wave of varying frequency. THx acts as an 8-bit counter. The following formula gives the output frequency for Timer 0 in PWM Mode 2. Mode 2: Oscillator Frequency 1 f out = ------------------------------------------------------ x -------------------2 x ( 256 - TH0 ) TPS + 1 Figure 14-8. Timer/Counter 1 PWM Mode 2 TH1 (8 Bits) OSC /TPS Control TL1 (8 Bits) T1 TR1 GATE INT1 Pin Note: {RH0 & RL0}/{RH1 & RL1} are not required by Timer 0/Timer 1 during PWM Mode 2 and may be used as temporary storage registers. 34 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 14.5.4 Mode 3 - Split 8-bit PWM Timer 1 in PWM Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in PWM Mode 3 establishes TL0 and TH0 as two separate PWM counters in a manner similar to normal Mode 3. PWM Mode 3 on Timer 0 is shown in Figure 14-9. Only the Timer Prescaler is available to change the output frequency during PWM Mode 3. TL0 can use the Timer 0 control bits: GATE, TR0, INT0, PWM0EN and TF0. TH0 is locked into a timer function and uses TR1, PWM1EN and TF1. RL0 provides the duty cycle for TL0 and RH0 provides the duty cycle for TH0. PWM Mode 3 is for applications requiring a single PWM channel and two timers, or two PWM channels and an extra timer or counter. With Timer 0 in PWM Mode 3, the AT89LP213 can appear to have three Timer/Counters. When Timer 0 is in PWM Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt. The following formulas give the output frequency and duty cycle for Timer 0 in PWM Mode 3. Mode 3: Oscillator Frequency 1 f out = ------------------------------------------------------ x -------------------256 TPS + 1 Mode 3, T0: Duty Cycle % = 100 x ---------256 Duty Cycle % = 100 x ----------256 RL0 Mode 3, T1: RH0 Figure 14-9. Timer/Counter 0 PWM Mode 3 RL0 (8 Bits) OCR0 = T0 OSC /TPS Control TL0 (8 Bits) TR1 GATE RH0 (8 Bits) OCR1 INT1 Pin = T1 OSC /TPS TH0 (8 Bits) TR1 35 3538A-MICRO-7/06 15. External Interrupts When the AT89LP213/214 is configured to use the internal RC Oscillator, XTAL1 and XTAL2 may be used as the INT0 and INT1 external interrupt sources. The external interrupts can be programmed to be level-activated or transition-activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx = 0, external interrupt x is triggered by a detected low at the INTx pin. If ITx = 1, external interrupt x is edge-triggered. In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle, interrupt request flag IEx in TCON is set. Flag bit IEx then requests the interrupt. Since the external interrupt pins are sampled once each clock cycle, an input high or low should hold for at least 2 oscillator periods to ensure sampling. If the external interrupt is transition-activated, the external source has to hold the request pin high for at least two clock cycles, and then hold it low for at least two clock cycles to ensure that the transition is seen so that interrupt request flag IEx will be set. IEx will be automatically cleared by the CPU when the service routine is called if generated in edge-triggered mode. If the external interrupt is level-activated, the external source has to hold the request active until the requested interrupt is actually generated. Then the external source must deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. 16. General-purpose Interrupts The General-purpose Interrupt (GPI) function provides 8 configurable external interrupts on Port 1. Each port pin can detect high/low levels or positive/negative edges. The GPIEN register select which bits of Port 1 are enabled to generate an interrupt. The GPMOD and GPLS registers determine the mode for each individual pin. GPMOD selects between level-sensitive and edge-triggered mode. GPLS selects between high/low in level mode and positive/negative in edge mode. The pins of Port 1 are sampled every clock cycle. In level-sensitive mode, a valid level must appear in two successive samples before generating the interrupt. In edge-triggered mode, a transition will be detected if the value changes from one sample to the next. When an interrupt condition on a pin is detected, and that pin is enabled, the appropriate flag in the GPIF register is set. The flags in GPIF must be cleared by software. . Table 16-1. GPMOD - General-purpose Interrupt Mode Register Reset Value = 0000 0000B GPMOD = 9AH Not Bit Addressable GPMOD7 Bit 7 GPMOD6 6 GPMOD5 5 GPMOD4 4 GPMOD3 3 GPMOD2 2 GPMOD1 1 GPMOD0 0 GPMOD.x 0 = level-sensitive interrupt for P1.x 1 = edge-triggered interrupt for P1.x 36 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] Table 16-2. GPLS - General-purpose Interrupt Level Select Register Reset Value = 0000 0000B GPLS = 9BH Not Bit Addressable GPLS7 Bit 7 GPLS6 6 GPLS5 5 GPLS4 4 GPLS3 3 GPLS2 2 GPLS1 1 GPLS0 0 GPMOD.x 0 = detect low level or negative edge on P1.x 1 = detect high level or positive edge on P1.x . Table 16-3. GPIEN - General-purpose Interrupt Enable Register Reset Value = 0000 0000B GPIEN = 9CH Not Bit Addressable GPIEN7 Bit 7 GPIEN6 6 GPIEN5 5 GPIEN4 4 GPIEN3 3 GPIEN2 2 GPIEN1 1 GPIEN0 0 GPIEN.x 0 = interrupt for P1.x disabled 1 = interrupt for P1.x enabled . Table 16-4. GPIF - General-purpose Interrupt Flag Register Reset Value = 0000 0000B GPIF = 9DH Not Bit Addressable GPIF7 Bit 7 GPIF6 6 GPIF5 5 GPIF4 4 GPIF3 3 GPIF2 2 GPIF1 1 GPIF0 0 GPIF.x 0 = interrupt on P1.x inactive 1 = interrupt on P1.x active. Must be cleared by software. 37 3538A-MICRO-7/06 17. Serial Interface The serial interface on the AT89LP214 implements a Universal Asynchronous Receiver/Transmitter (UART). The UART has the following features: * Full Duplex Operation * 8 or 9 Data Bits * Framing Error Detection * Multiprocessor Communication Mode with Automatic Address Recognition * Baud Rate Generator Using Timer 1 * Interrupt on Receive Buffer Full or Transmission Complete The serial interface is full duplex, which means it can transmit and receive simultaneously. It is also receive-buffered, which means it can begin receiving a second byte before a previously received byte has been read from the receive register. (However, if the first byte still has not been read when reception of the second byte is complete, one of the bytes will be lost.) The serial port receive and transmit registers are both accessed at the Special Function Register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The serial port can operate in the following four modes. * Mode 0: Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted/received, with the LSB first. The baud rate is fixed at 1/2 the oscillator frequency. * Mode 1: 10 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in the Special Function Register SCON. The baud rate is variable based on Timer 1. * Mode 2: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8 in SCON) can be assigned the value of "0" or "1". For example, the parity bit (P, in the PSW) can be moved into TB8. On receive, the 9th data bit goes into RB8 in the Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/16 or 1/32 the oscillator frequency. * Mode 3: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except the baud rate, which is variable based on Timer 1 in Mode 3. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. 17.1 Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received, followed by a stop bit. The 9th bit goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt is activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. The following example shows how to use the serial interrupt for multiprocessor communications. When the master processor must transmit a block of data to one of several slaves, it first sends out an address byte that identifies the target slave. An address byte differs from a data byte in that the 9th bit is "1" in an address byte and "0" in a data byte. With SM2 = 1, no slave is interrupted by a data byte. An address byte, however, interrupts all slaves. Each slave can examine the received byte and see if it is being addressed. The addressed slave clears its SM2 38 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] bit and prepares to receive the data bytes that follows. The slaves that are not addressed set their SM2 bits and ignore the data bytes. The SM2 bit has no effect in Mode 0 but can be used to check the validity of the stop bit in Mode 1. In a Mode 1 reception, if SM2 = 1, the receive interrupt is not activated unless a valid stop bit is received. Table 17-1. SCON - Serial Port Control Register Reset Value = 0000 0000B SCON Address = 98H Bit Addressable SM0/FE Bit 7 (SMOD0 = 0/1) Symbol FE SM0 (1) SM1 6 SM2 5 REN 4 TB8 3 RB8 2 T1 1 RI 0 Function Framing error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid frames and must be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. FE will be set regardless of the state of SMOD0. Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0) Serial Port Mode Bit 1 SM0 0 SM1 0 1 0 1 Mode 0 1 2 3 Description shift register 8-bit UART 9-bit UART 9-bit UART Baud Rate(2) fosc/2 variable (Timer 1) fosc/32 or fosc/16 variable (Timer 1) SM1 0 1 1 SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. Enables serial reception. Set by software to enable reception. Clear by software to disable reception. The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. 1. SMOD0 is located at PCON.6. 2. fosc = oscillator frequency. REN TB8 RB8 TI RI Notes: 39 3538A-MICRO-7/06 17.2 Baud Rates The baud rate in Mode 0 is fixed as shown in the following equation: Oscillator Frequency Mode 0 Baud Rate = -----------------------------------------------------2 The baud rate in Mode 2 depends on the value of the SMOD1 bit in Special Function Register PCON.7. If SMOD1 = 0 (the value on reset), the baud rate is 1/32 of the oscillator frequency. If SMOD1 = 1, the baud rate is 1/16 of the oscillator frequency, as shown in the following equation: 2 Mode 2 Baud Rate = ------------------- x (Oscillator Frequency) 32 SMOD1 17.2.1 Using Timer 1 to Generate Baud Rates The Timer 1 overflow rate determines the baud rates in Modes 1 and 3. When Timer 1 is the baud rate generator, the baud rates are determined by the Timer 1 overflow rate and the value of SMOD1 according to the following equation: Modes 1, 3 2 = ------------------- x (Timer 1 Overflow Rate) 32 Baud Rate SMOD1 The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either timer or counter operation in any of its 3 running modes. In the most typical applications, it is configured for timer operation in auto-reload mode (high nibble of TMOD = 0010B). In this case, the baud rate is given by the following formula: Modes 1, 3 2 1- Oscillator Frequency = ------------------- x ------------------------------------------------------ x ------------------32 [ 256 - ( TH1 ) ] TPS + 1 Baud Rate SMOD1 Programmers can achieve very low baud rates with Timer 1 by configuring the Timer to run as a 16-bit auto-reload timer (high nibble of TMOD = 0001B). In this case, the baud rate is given by the following formula. Modes 1, 3 2 Oscillator Frequency 1 = ------------------- x ------------------------------------------------------ x ------------------32 [ 256 - ( RH1,RL1 ) ] TPS + 1 Baud Rate SMOD1 Table 17-2 lists commonly used baud rates and how they can be obtained from Timer 1. Table 17-2. Baud Rate Mode 0: 1 MHz Mode 2: 375K 62.5K 19.2K 9.6K 4.8K 2.4K 1.2K 137.5 110 110 Commonly Used Baud Rates Generated by Timer 1 (TPS = 0000B) Timer 1 fOSC (MHz) 2 12 12 11.059 11.059 11.059 11.059 11.059 11.986 6 12 SMOD1 X 0 1 1 0 0 0 0 0 0 0 C/T X X 0 0 0 0 0 0 0 0 0 Mode X X 2 2 2 2 2 1 1 1 1 Reload Value X X F4H DCH DCH B8H 70H FEE0H F55CH F958H F304H 40 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 17.3 More About Mode 0 Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted/received, with the LSB first. The baud rate is fixed at 1/2 the oscillator frequency. Figure 17-1 on page 42 shows a simplified functional diagram of the serial port in Mode 0 and associated timing. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF" signal also loads a "1" into the 9th position of the transmit shift register and tells the TX Control Block to begin a transmission. The internal timing is such that one full machine cycle will elapse between "write to SBUF" and activation of SEND. SEND transfers the output of the shift register to the alternate output function line of P3.0, and also transfers Shift Clock to the alternate output function line of P3.1. At the falling edge of Shift Clock the contents of the transmit shift register are shifted one position to the right. As data bits shift out to the right, "0"s come in from the left. When the MSB of the data byte is at the output position of the shift register, the "1" that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain "0"s. This condition flags the TX Control block to do one last shift, then deactivate SEND and set TI. Reception is initiated by the condition REN = 1 and R1 = 0. At the next clock cycle, the RX Control unit writes the bits 11111110 to the receive shift register and activates RECEIVE in the next clock phase. RECEIVE enables Shift Clock to the alternate output function line of P3.1. At the falling edge of Shift Clock the contents of the receive shift register are shifted one position to the left. The value that comes in from the right is the value that was sampled at the P3.0 pin at rising edge of Shift Clock. As data bits come in from the right, "1"s shift out to the left. When the "0" that was initially loaded into the right-most position arrives at the left-most position in the shift register, it flags the RX Control block to do one last shift and load SBUF. Then RECEIVE is cleared and RI is set. 41 3538A-MICRO-7/06 Figure 17-1. Serial Port Mode 0 INTERNAL BUS "1" 1/2 fosc INTERNAL BUS WRITE TO SBUF SEND SHIFT RXD (DATA OUT) TXD (SHIFT CLOCK) TI WRITE TO SCON (CLEAR RI) RI RECEIVE SHIFT RXD (DATA IN) TXD (SHIFT CLOCK) 42 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 17.4 More About Mode 1 Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the AT89LP214, the baud rate is determined by the Timer 1 overflow rate. Figure 17-2 shows a simplified functional diagram of the serial port in Mode 1 and associated timings for transmit and receive. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF" signal also loads a "1" into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. Thus, the bit times are synchronized to the divide-by-16 counter, not to the "write to SBUF" signal. The transmission begins when SEND is activated, which puts the start bit at TXD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TXD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, "0"s are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, the "1" that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain "0"s. This condition flags the TX Control unit to do one last shift, then deactivate SEND and set TI. This occurs at the tenth divide-by-16 rollover after "write to SBUF." Reception is initiated by a 1-to-0 transition detected at RXD. For this purpose, RXD is sampled at a rate of 16 times the established baud rate. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its roll-overs with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RXD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done to reject noise. In order to reject false bits, if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit continues looking for another l-to-0 transition. If the start bit is valid, it is shifted into the input shift register, and reception of the rest of the frame proceeds. As data bits come in from the right, "1"s shift out to the left. When the start bit arrives at the leftmost position in the shift register, (which is a 9-bit register in Mode 1), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8 and to set RI is generated if, and only if, the following conditions are met at the time the final shift pulse is generated. RI = 0 and Either SM2 = 0, or the received stop bit = 1 If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, whether or not the above conditions are met, the unit continues looking for a 1-to-0 transition in RXD. 43 3538A-MICRO-7/06 Figure 17-2. Serial Port Mode 1 TIMER 1 OVERFLOW "1" INTERNAL BUS /2 SMOD1 =0 SMOD1 =1 WRITE TO SBUF S DQ CL SBUF ZERO DETECTOR TXD START SHIFT DATA TX CONTROL TI SEND /16 SERIAL PORT INTERRUPT RX CLOCK /16 SAMPLE 1-TO-0 TRANSITION DETECTOR RX CLOCK RI START RX CONTROL LOAD SBUF SHIFT 1FFH BIT DETECTOR INPUT SHIFT REG. (9 BITS) RXD LOAD SBUF SHIFT SBUF READ SBUF INTERNAL BUS TX CLOCK WRITE TO SBUF SEND DATA SHIFT TXD TI D0 D1 D2 D3 D4 D5 D6 D7 START BIT RX CLOCK STOP BIT /16 RESET RECEIVE RXD START BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT BIT DETECTOR SAMPLE TIMES SHIFT RI 44 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 TRANSMIT AT89LP213/214 [Preliminary] 17.5 More About Modes 2 and 3 Eleven bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of "0" or "1". On receive, the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/16 or 1/32 of the oscillator frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1. Figures 17-3 and 17-4 show a functional diagram of the serial port in Modes 2 and 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF" signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. Thus, the bit times are synchronized to the divide-by-16 counter, not to the "write to SBUF" signal. The transmission begins when SEND is activated, which puts the start bit at TXD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TXD. The first shift pulse occurs one bit time after that. The first shift clocks a "1" (the stop bit) into the 9th bit position of the shift register. Thereafter, only "0"s are clocked in. Thus, as data bits shift out to the right, "0"s are clocked in from the left. When TB8 is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that contain "0"s. This condition flags the TX Control unit to do one last shift, then deactivate SEND and set TI. This occurs at the 11th divide-by-16 rollover after "write to SBUF." Reception is initiated by a 1-to-0 transition detected at RXD. For this purpose, RXD is sampled at a rate of 16 times the established baud rate. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift register. At the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RXD. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit continues looking for another l-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame proceeds. As data bits come in from the right, "1"s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8 and to set RI is generated if, and only if, the following conditions are met at the time the final shift pulse is generated: RI = 0, and Either SM2 = 0 or the received 9th data bit = 1 If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit continues looking for a 1-to-0 transition at the RXD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8, or RI. 45 3538A-MICRO-7/06 Figure 17-3. Serial Port Mode 2 INTERNAL BUS CPU CLOCK SMOD1 1 SMOD1 0 INTERNAL BUS 46 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] Figure 17-4. Serial Port Mode 3 TIMER 1 OVERFLOW INTERNAL BUS TB8 /2 SMOD1 =0 SMOD1 =1 WRITE TO SBUF S DQ CL SBUF ZERO DETECTOR TXD /16 SERIAL PORT INTERRUPT SHIFT DATA START STOP BIT TX CONTROL RX CLOCK SEND TI /16 SAMPLE 1-TO-0 TRANSITION DETECTOR RX CLOCK RI START RX CONTROL LOAD SBUF SHIFT 1FFH BIT DETECTOR INPUT SHIFT REG. (9 BITS) RXD LOAD SBUF SHIFT SBUF READ SBUF TX CLOCK WRITE TO SBUF SEND DATA SHIFT TXD TI D0 D1 D2 D3 D4 INTERNAL BUS D5 D6 D7 TB8 START BIT STOP BIT STOP BIT GEN RX CLOCK RXD RECEIVE /16 RESET START BIT D0 D1 D2 D3 D4 D5 D6 D7 RB8 BIT DETECTOR SAMPLE TIMES SHIFT RI STOP BIT TRANSMIT 47 3538A-MICRO-7/06 17.6 Framing Error Detection In addition to all of its usual modes, the UART can perform framing error detection by looking for missing stop bits, and automatic address recognition. When used for framing error detect, the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE, SCON.7 can only be cleared by software. 17.7 Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9th bit UART modes, Mode 2 and Mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the "Given" address or the "Broadcast" address. The 9th bit mode requires that the 9th information bit to be a "1" to indicate that the received information is an address and not data. The 8th bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8th address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave's address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are "don't care". The SADEN mask can be logically ANDed with the SADDR to create the "Given" address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples show the versatility of this scheme: Slave 0 SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00X0 Slave 1 SADDR = 1100 0000 SADEN = 1111 1110 Given = 1100 000X In the previous example, SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a "0" in bit 0 and it ignores bit 1. Slave 1 requires a "0" in bit 1 and bit 0 is ignored. A unique address for slave 0 would be 1100 0010 since slave 1 requires a "0" in bit 1. A unique address for slave 1 would be 1100 0001 since a "1" in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. 48 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] In a more complex system, the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = 1100 0000 SADEN = 1111 1001 Given = 1100 0XX0 Slave 1 SADDR = 1110 0000 SADEN = 1111 1010 Given = 1110 0X0X Slave 2 SADDR = 1110 0000 SADEN = 1111 1100 Given = 1110 00XX In the above example, the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2, use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logic OR of SADDR and SADEN. Zeros in this result are trended as don't cares. In most cases, interpreting the don't cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are loaded with "0"s. This produces a given address of all "don't cares" as well as a Broadcast address of all "don't cares". This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51-type UART drivers which do not make use of this feature. 18. Serial Peripheral Interface The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the AT89LP213/214 and peripheral devices or between multiple AT89LP213/214 devices. The SPI features include the following: * Full-duplex, 3-wire Synchronous Data Transfer * Master or Slave Operation * Maximum Bit Frequency = fOSC/4 * LSB First or MSB First Data Transfer * Four Programmable Bit Rates in Master Mode * End of Transmission Interrupt Flag * Write Collision Flag Protection * Double-buffered Receive * Double-buffered Transmit (Enhanced Mode Only) * Wake up from Idle Mode (Slave Mode Only) 49 3538A-MICRO-7/06 The interconnection between master and slave CPUs with SPI is shown in Figure 18-1. The four pins in the interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift Clock (SCK), and Slave Select (SS). The SCK pin is the clock output in master mode, but is the clock input in slave mode. The MSTR bit in SPCR determines the directions of MISO and MOSI. Also notice that MOSI connects to MOSI and MISO to MISO. In master mode, SS/P1.4 is ignored and may be used as a general-purpose input or output. In slave mode, SS must be driven low to select an individual device as a slave. When SS is driven high, the slave's SPI port is deactivated and the MOSI/P1.5 pin can be used as a general-purpose input. Figure 18-1. SPI Master-slave Interconnection MSB Master LSB MISO MISO MSB Slave LSB 8-Bit Shift Register MOSI MOSI 8-Bit Shift Register SPI Clock Generator SCK SS VCC SCK SS The SPI has two modes of operation: normal (non-buffered write) and enhanced (buffered write). In normal mode, writing to the SPI data register (SPDR) of the master CPU starts the SPI clock generator and the data written shifts out of the MOSI pin and into the MOSI pin of the slave CPU. Transmission may start after an initial delay while the clock generator waits for the next full bit slot of the specified baud rate. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF) and transferring the received byte to the read buffer (SPDR). If both the SPI interrupt enable bit (SPIE) and the serial port interrupt enable bit (ES) are set, an interrupt is requested. Note that SPDR refers to either the write data buffer or the read data buffer, depending on whether the access is a write or read. In normal mode, because the write buffer is transparent (and a write access to SPDR will be directed to the shift buffer), any attempt to write to SPDR while a transmission is in progress will result in a write collision with WCOL set. However, the transmission will still complete normally, but the new byte will be ignored and a new write access to SPDR will be necessary. Enhanced mode is similar to normal mode except that the write buffer holds the next byte to be transmitted. Writing to SPDR loads the write buffer and sets WCOL to signify that the buffer is full and any further writes will overwrite the buffer. WCOL is cleared by hardware when the buffered byte is loaded into the shift register and transmission begins. If the master SPI is currently idle, i.e. if this is the first byte, then after loading SPDR, transmission of the byte starts and WCOL is cleared immediately. While this byte is transmitting, the next byte may be written to SPDR. The Load Enable flag (LDEN) in SPSR can be used to determine when transmission has started. LDEN is asserted during the first four bit slots of a SPI transfer. The master CPU should first check that LDEN is set and that WCOL is cleared before loading the next byte. In enhanced mode, if WCOL is set when a transfer completes, i.e. the next byte is available, then the SPI immediately loads the buffered byte into the shift register, resets WCOL, and continues transmission without stopping and restarting the clock generator. As long as the CPU can keep the write buffer full in this manner, multiple bytes may be transferred with minimal latency between bytes. 50 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] Table 18-1. SPCR - SPI Control Register Reset Value = 0000 0000B SPCR Address = E9H Not Bit Addressable SPIE Bit Symbol SPIE SPE DORD MSTR CPOL CPHA 7 Function SPE 6 DORD 5 MSTR 4 CPOL 3 CPHA 2 SPR1 1 SPR0 0 SPI interrupt enable. This bit, in conjunction with the ES bit in the IE register, enables SPI interrupts: SPIE = 1 and ES = 1 enable SPI interrupts. SPIE = 0 disables SPI interrupts. SPI enable. SPI = 1 enables the SPI channel and connects SS, MOSI, MISO and SCK to pins P1.4, P1.5, P1.6, and P1.7. SPI = 0 disables the SPI channel. Data order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission. Master/slave select. MSTR = 1 selects Master SPI mode. MSTR = 0 selects slave SPI mode. Clock polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is low when not transmitting. Please refer to figure on SPI clock phase and polarity control. Clock phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between master and slave. Please refer to figure on SPI clock phase and polarity control. SPI clock rate select. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK and the oscillator frequency, FOSC., is as follows: SPR1 SPR0 0 1 0 1 SCK fOSC/4 fOSC/8 fOSC/32 fOSC/64 SPR0 SPR1 0 0 1 1 Notes: 1. Set up the clock mode before enabling the SPI: set all bits needed in SPCR except the SPE bit, then set SPE. 2. Enable the master SPI prior to the slave device. 3. Slave echoes master on the next Tx if not loaded with new data. Table 18-2. SPDR - SPI Data Register Reset Value = 00H (after cold reset) unchanged (after warm reset) SPDR Address = EAH Not Bit Addressable SPD7 Bit 7 SPD6 6 SPD5 5 SPD4 4 SPD3 3 SPD2 2 SPD1 1 SPD0 0 51 3538A-MICRO-7/06 Table 18-3. SPSR - SPI Status Register Reset Value = 000X X000B SPSR Address = E8H Not Bit Addressable SPIF Bit Symbol SPIF 7 Function WCOL 6 LDEN 5 - 4 - 3 SSIG 2 DISSO 1 ENH 0 SP interrupt flag. When a serial transfer is complete, the SPIF bit is set and an interrupt is generated if SPIE = 1 and ES = 1. The SPIF bit is cleared by reading the SPI status register followed by reading/writing the SPI data register. When ENH = 0: Write collision flag. The WCOL bit is set if the SPI data register is written during a data transfer. During data transfer, the result of reading the SPDR register may be incorrect, and writing to it has no effect. The WCOL bit (and the SPIF bit) are cleared by reading the SPI status register followed by reading/writing the SPI data register. When ENH = 1: WCOL works in Enhanced mode as Tx Buffer Full. Writing during WCOL = 1 in enhanced mode will overwrite the waiting data already present in the Tx Buffer. In this mode, WCOL is no longer reset by the SPIF reset but is reset when the write buffer has been unloaded into the serial shift register. Load enable for the Tx buffer in enhanced SPI mode. When ENH is set, it is safe to load the Tx Buffer while LDEN = 1 and WCOL = 0. LDEN is high during bits 0 - 3 and is low during bits 4 - 7 of the SPI serial byte transmission time frame. Slave Select Ignore. If SSIG = 0, the SPI will only operate in slave mode if SS (P1.4) is pulled low. When SSIG = 1, the SPI ignores SS in slave mode and is active whenever SPE (SPCR.6) is set. P1.4 may be used as a regular I/O pin when SSIG = 1. Disable slave output bit. When set, this bit causes the MISO pin to be tri-stated so more than one slave device can share the same interface with a single master. Normally, the first byte in a transmission could be the slave address and only the selected slave should clear its DISSO bit. Enhanced SPI mode select bit. When ENH = 0, SPI is in normal mode, i.e. without write double buffering. When ENH = 1, SPI is in enhanced mode with write double buffering. The Tx buffer shares the same address with the SPDR register. WCOL LDEN SSIG DISSO ENH 52 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] Figure 18-2. SPI Shift Register Diagram 7 Serial In 8 Serial Master 2:1 MUX D LATCH CLK Q 2:1 MUX Serial Slave D LATCH CLK Q Serial Out 8 Parallel Master Transmit Byte (Write Buffer) 8 Parallel Slave (Read Buffer) 8 D LATCH CLK Q D LATCH CLK Q 8 Receive Byte Figure 18-3. SPI Block Diagram S Oscillator MSB 8-bit Shift Register M M LSB Read Data Buffer Write Data Buffer MISO P1.6 MOSI P1.5 S Divider /4/8/32/64 SPI Clock (Mater) Clock Clock Logic S M Pin Control Logic Select SPR1 SPR0 SCK 1.7 SS P1.4 SPI Control WCOL SPIF MSTR SPE DORD MSTR CPHA CPOL SPR1 SPR0 SPIE 8 SPI Status Register SPE SPI Control Register 8 8 SPI Interrupt Request Internal Data Bus DORD MSTR SPE 53 3538A-MICRO-7/06 The CPHA (Clock PHAse), CPOL (Clock POLarity), and SPR (Serial Peripheral clock Rate = baud rate) bits in SPCR control the shape and rate of SCK. The two SPR bits provide four possible clock rates when the SPI is in master mode. In slave mode, the SPI will operate at the rate of the incoming SCK as long as it does not exceed the maximum bit rate. There are also four possible combinations of SCK phase and polarity with respect to the serial data. CPHA and CPOL determine which format is used for transmission. The SPI data transfer formats are shown in Figures 18-4 and 18-5. To prevent glitches on SCK from disrupting the interface, CPHA, CPOL, and SPR should not be modified while the interface is enabled, and the master device should be enabled before the slave device(s). Figure 18-4. SPI Transfer Format with CPHA = 0 Note: *Not defined but normally MSB of character just received. Figure 18-5. SPI Transfer Format with CPHA = 1 SCK CYCLE # (FOR REFERENCE) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (FROM MASTER) MISO (FROM SLAVE) SS (TO SLAVE) MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB 1 2 3 4 5 6 7 8 * MSB Note: *Not defined but normally LSB of previously transmitted character. 54 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 19. Analog Comparator A single analog comparator is provided on the AT89LP213/214. The analog comparator has the following features: * Comparator Output Flag and Interrupt * Selectable Interrupt Condition - High- or Low-level - Rising- or Falling-edge - Output Toggle * Hardware Debouncing Modes Comparator operation is such that the output is a logic "1" when the positive input AIN0 (P1.0]) is greater than the negative input AIN1 (P1.1). Otherwise the output is a zero. Setting the CEN bit in ACSR enables the comparator. When the comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 s. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. Before enabling the comparator the analog inputs should be tristated by putting P1.0 and P1.1 into input-only mode. See "Port 1 Analog Functions" on page 25. The comparator may be configured to cause an interrupt under a variety of output value conditions by setting the CM bits in ACSR. The comparator interrupt flag CF in ACSR is set whenever the comparator output matches the condition specified by CM. The flag may be polled by software or may be used to generate an interrupt and must be cleared by software. 19.1 Comparator Interrupt with Debouncing The comparator output is sampled every clock cycle. The conditions on the analog inputs may be such that the comparator output will toggle excessively. This is especially true if applying slow moving analog inputs. Three debouncing modes are provided to filter out this noise. In debouncing mode, the comparator uses Timer 1 to modulate its sampling time. When a relevant transition occurs, the comparator waits until two Timer 1 overflows have occurred before resampling the output. If the new sample agrees with the expected value, CF is set. Otherwise, the event is ignored. The filter may be tuned by adjusting the time-out period of Timer 1. Because Timer 1 is free running, the debouncer must wait for two overflows to guarantee that the sampling delay is at least 1 time-out period. Therefore, after the initial edge event, the interrupt may occur between 1 and 2 time-out periods later. See Figure 19-1 on page 55. By default the comparator is disabled during Idle mode. To allow the comparator to function during Idle, the CIDL bit is ACSR must be set. When CIDL is set, the comparator can be used to wake-up the CPU from Idle if the comparator interrupt is enabled. The comparator is always disabled during Power-down mode. Figure 19-1. Negative Edge with Debouncing Example Comparator Out Timer 1 Overflow CF Start Compare Start Compare 55 3538A-MICRO-7/06 Table 19-1. ACSR - Analog Comparator Control & Status Register Reset Value = XXX0 0000B ACSR = 97H Not Bit Addressable - Bit Symbol CIDL CF CEN 7 Function - 6 CIDL 5 CF 4 CEN 3 CM3 2 CM1 1 CM0 0 Comparator Idle Enable. If CIDL = 1 the comparator will continue to operate during Idle mode. If CIDL = 0 the comparator is powered down during Idle mode. The comparator is always shut down during Power-down mode. Comparator Interrupt Flag. Set when the comparator output meets the conditions specified by the CM [2:0] bits and CEN is set. The flag must be cleared by software. The interrupt may be enabled/disabled by setting/clearing bit 6 of IE. Comparator Enable. Set this bit to enable the comparator. Clearing this bit will force the comparator output low and prevent further events from setting CF. When CEN = 1 the analog input pins, P1.0 and P1.1, have their digital inputs disabled. Comparator Interrupt Mode CM2 0 0 0 0 1 1 1 1 CM1 0 0 1 1 0 0 1 1 CM0 0 1 0 1 0 1 0 1 Interrupt Mode Negative (Low) level Positive edge Toggle with debouncing(1) Positive edge with debouncing(1) Negative edge Toggle Negative edge with debouncing(1) Positive (High) level CM [2:0] Note: 1. Debouncing modes require the use of Timer 1 to generate the sampling delay. 56 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 20. Programmable Watchdog Timer The programmable Watchdog Timer (WDT) protects the system from incorrect execution by triggering a system reset when it times out after the software has failed to feed the timer prior to the timer overflow. By Default the WDT counts CPU clock cycles. The prescaler bits, PS0, PS1 and PS2 in SFR WDTCON are used to set the period of the Watchdog Timer from 16K to 2048K clock cycles. The Timer Prescaler can also be used to lengthen the time-out period (see Table 9-2 on page 13) The WDT is disabled by Reset and during Power-down mode. When the WDT times out without being serviced, an internal RST pulse is generated to reset the CPU. See Table 20-1 for the available WDT period selections. Table 20-1. Watchdog Timer Time-out Period Selection WDT Prescaler Bits PS2 0 0 0 0 1 1 1 1 Note: PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 Period(1) (Clock Cycles) 16K 32K 64K 128K 256K 512K 1024K 2048K 1. The WDT time-out period is dependent on the system clock frequency. 2 Time-out Period = ------------------------------------------------------ x ( TPS + 1 ) Oscillator Frequency The Watchdog Timer consists of a 14-bit timer with 7-bit programmable prescaler. Writing the sequence 1EH/E1H to the WDTRST register enables the timer. When the WDT is enabled, the WDTEN bit in WDTCON will be set to "1". To prevent the WDT from generating a reset when if overflows, the watchdog feed sequence must be written to WDTRST before the end of the timeout period. To feed the watchdog, two write instructions must be sequentially executed successfully. Between the two write instructions, SFR reads are allowed, but writes are not allowed. The instructions should move 1EH to the WDTRST register and then 1EH to the WDTRST register. An incorrect feed or enable sequence will cause an immediate watchdog reset. The program sequence to feed or enable the watchdog timer is as follows: MOV WDTRST, #01Eh MOV WDTRST, #0E1h ( PS + 14 ) 57 3538A-MICRO-7/06 20.1 Software Reset A Software Reset of the AT89LP213/214 is accomplished by writing the software reset sequence 5AH/A5H to the WDTRST SFR. The WDT does not need to be enabled to generate the software reset. A normal software reset will set the SWRST flag in WDTCON. However, if at any time an incorrect sequence is written to WDTRST (i.e. anything other than 1EH/E1H or 5AH/A5H), a software reset will immediately be generated and both the SWRST and WDTOVF flags will be set. In this manner an intentional software reset may be distinguished from a software error-generated reset. The program sequence to generate a software reset is as follows: MOV WDTRST, #05Ah MOV WDTRST, #0A5h Table 20-2. WDTCON - Watchdog Control Register Reset Value = 0000 X000B WDTCON Address = A7H Not Bit Addressable PS2 Bit Symbol PS2 PS1 PS0 WDIDLE SWRST WDTOVF WDTEN 7 Function PS1 6 PS0 5 WDIDLE 4 - 3 SWRST 2 WDTOVF 1 WDTEN 0 Prescaler bits for the watchdog timer (WDT). When all three bits are cleared to 0, the watchdog timer has a nominal period of 16K clock cycles. When all three bits are set to 1, the nominal period is 2048K clock cycles. Disable/enable the Watchdog Timer in IDLE mode. When WDIDLE = 0, WDT continues to count in IDLE mode. When WDIDLE = 1, WDT freezes while the device is in IDLE mode. Software Reset Flag. Set when a software reset is generated by writing the sequence 5AH/A5H to WDTRST. Also set when an incorrect sequence is written to WDTRST. Must be cleared by software. Watchdog Overflow Flag. Set when a WDT rest is generated by the WDT timer overflow. Also set when an incorrect sequence is written to WDTRST. Must be cleared by software. Watchdog Enable Flag. This bit is READ-ONLY and reflects the status of the WDT (whether it is running or not). The WDT is disabled after any reset and must be re-enabled by writing 1EH/E1H to WDTRST Table 20-3. WDTRST - Watchdog Reset Register (Write-Only) WDTCON Address = A6H Not Bit Addressable - Bit 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 The WDT is enabled by writing the sequence 1EH/E1H to the WDTRST SFR. The current status may be checked by reading the WDTEN bit in WDTCON. To prevent the WDT from resetting the device, the same sequence 1EH/E1H must be written to WDTRST before the time-out interval expires. A software reset is generated by writing the sequence 5AH/A5H to WDTRST. 58 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 21. Instruction Set Summary The AT89LP213/214 is fully binary compatible with the MCS-51 instruction set. The difference between the AT89LP213/214 and the standard 8051 is the number of cycles required to execute an instruction. Instructions in the AT89LP213/214 may take 1, 2, 3 or 4 clock cycles to complete. The execution times of most instructions may be computed using Table 21-1. Table 21-1. Instruction Execution Times and Exceptions Cycle Count Formula # bytes # bytes + 1 2 4 3 4 2 4 2 Clock Cycles Arithmetic ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @Ri ADDC A, #data SUBB A, Rn SUBB A, direct SUBB A, @Ri SUBB A, #data INC Rn INC direct INC @Ri INC A DEC Rn DEC direct DEC @Ri DEC A Bytes 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 8051 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 AT89LP 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 2 Hex Code 28-2F 25 26-27 24 38-3F 35 36-37 34 98-9F 95 96-97 94 08-0F 05 06-07 04 18-1F 15 16-17 14 Generic Instruction Types Most arithmetic, logical, bit and transfer instructions Branches and Calls Single Byte Indirect (i.e. ADD A, @Ri, etc.) RET, RETI MOVC MOVX MUL DIV INC DPTR 59 3538A-MICRO-7/06 Table 21-1. Instruction Execution Times and Exceptions (Continued) Clock Cycles Arithmetic INC DPTR MUL AB DIV AB DA A Bytes 1 1 1 1 8051 24 48 48 12 AT89LP 2 2 4 1 Hex Code A3 A4 84 D4 Clock Cycles Logical CLR A CPL A ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data RL A RLC A RR A RRC A SWAP A Bytes 1 1 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 8051 12 12 12 12 12 12 12 24 12 12 12 12 12 24 12 12 12 12 12 24 12 12 12 12 12 AT89LP 1 1 1 2 2 2 2 3 1 2 2 2 2 3 1 2 2 2 2 3 1 1 1 1 1 Hex Code E4 F4 58-5F 55 56-57 54 52 53 48-4F 45 46-47 44 42 43 68-6F 65 66-67 64 62 63 23 33 03 13 C4 60 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] Table 21-1. Instruction Execution Times and Exceptions (Continued) Clock Cycles Data Transfer MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data MOV DPTR, #data16 MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @Ri MOVX A, @DPTR MOVX @Ri, A MOVX @DPTR, A PUSH direct POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit Bytes 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 1 2 1 2 1 2 2 8051 12 12 12 12 12 24 12 12 24 24 24 24 12 24 12 24 24 24 24 24 24 24 24 24 12 12 12 12 12 12 12 12 12 12 24 AT89LP 1 2 2 2 1 2 2 2 2 3 2 3 1 2 2 3 3 3 4 4 4 4 2 2 1 2 2 2 1 2 1 2 1 2 2 Hex Code E8-EF E5 E6-E7 74 F8-FF A8-AF 78-7F F5 88-8F 85 86-87 75 F6-F7 A6-A7 76-77 90 93 83 E2-E3 E0 F2-F3 F0 C0 D0 C8-CF C5 C6-C7 D6-D7 C3 C2 D3 D2 B3 B2 82 61 3538A-MICRO-7/06 Table 21-1. Instruction Execution Times and Exceptions (Continued) Clock Cycles Bit Operations ANL C, bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C Bytes 2 2 2 2 2 8051 24 24 24 12 24 AT89LP 2 2 2 2 2 Hex Code B0 72 A0 A2 92 Clock Cycles Branching JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel JZ rel JNZ rel SJMP rel ACALL addr11 LCALL addr16 RET RETI AJMP addr11 LJMP addr16 JMP @A+DPTR JMP @A+PC (1) Bytes 2 2 3 3 3 2 2 2 2 3 1 1 2 3 1 2 3 3 3 3 2 3 1 8051 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 - 24 24 24 24 24 24 12 - AT89LP 3 3 4 4 4 3 3 3 3 4 4 4 3 4 2 3 4 4 4 4 3 4 1 2 Hex Code 40 50 20 30 10 60 70 80 11,31,51,71,9 1,B1,D1,F1 12 22 32 01,21,41,61,8 1,A1,C1,E1 02 73 A5 73 B5 B4 B8-BF B6-B7 D8-DF D5 00 A5 00 CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel CJNE @Ri, #data, rel DJNZ Rn, rel DJNZ direct, rel NOP BREAK Note: (1) 2 1. This escaped instruction is an extension to the instruction set. 62 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 22. On-chip Debug System The AT89LP213/214 On-chip Debug (OCD) System uses a two-wire serial interface to control program flow; read, modify, and write the system state; and program the nonvolatile memory. The OCD System has the following features: * Complete program flow control * Read-modify-write access to all internal SFRs and data memories * Four hardware program address breakpoints * Unlimited program software breakpoints using BREAK instruction * Break on stack overflow/underflow * Break on Watchdog overflow * Non-intrusive operation * Programming of nonvolatile memory 22.1 Physical Interface The On-chip Debug System uses a two-wire synchronous serial interface to establish communication between the target device and the controlling emulator system. The OCD interface is controlled by two User Fuses. OCD is enabled by clearing the OCD Enable Fuse. When OCD is enabled, the RST port pin is configured as an input for the Debug Clock (DCL). Either the XTAL1 or XTAL2 pin is configured as a bi-directional data line for the Debug Data (DDA) depending on the clock source selected. If the External Clock is selected, XTAL2 is configured as DDA. If the Internal RC Oscillator is selected, XTAL1 is configured as DDA. The OCD device connections are shown in Figure 22-1. When OCD is enabled, the type of interface used depends on the OCD Interface Select User Fuse. This fuse selects between a normal two-wire interface (TWI) and a fast two-wire interface (FTWI). It is the duty of the user to program this fuse to the correct setting for their debug system at the same time they enable OCD (see "User Configuration Fuses" on page 71). Figure 22-1. AT89LP213/214 On-chip Debug Connections VCC DCL P1.3/RST DCL P1.3/RST VCC DDA XTAL1 GND CLK XTAL1 GND XTAL2 DDA CLK = Internal RC CLK = External Clock When designing a system where On-chip Debug will be used, the following observations must be considered for correct operation: * P1.3/RST cannot be connected directly to VCC and any external capacitors connect to RST must be removed. * All external reset sources must be removed. * The quartz crystal and any capacitors on XTAL1 or XTAL2 must be removed and an external clock signal must be driven on XTAL1 if the user does not wish to use the internal RC oscillator. Some emulator systems may provide a user-configurable clock for this purpose. 63 3538A-MICRO-7/06 22.2 Software Breakpoints The AT89LP213/214 microcontroller includes a BREAK instruction for implementing program memory breakpoints in software. A software breakpoint can be inserted manually by placing the BREAK instruction in the program code. Some emulator systems may allow for automatic insertion/deletion of software breakpoints. The Flash memory must be re-programmed each time a software breakpoint is changed. Frequent insertions/deletions of software breakpoints will reduce the data retention of the nonvolatile memory. Devices used for debugging purposes should not be shipped to end customers. The BREAK instruction is treated as a two-cycle NOP when OCD is disabled. 22.3 Limitations of On-chip Debug The AT89LP213/214 is a low-cost, low-pincount yet fully-featured microcontroller that multiplexes several functions on its limited I/O pins. Some device functionality must be sacrificed to provide resources for On-chip Debugging. The On-chip Debug System has the following limitations: * The Debug Clock pin (DCL) is physically located on that same pin as Port Pin P1.3 and the External Reset (RST). Therefore, neither P1.3 nor an external reset source may be emulated when OCD is enabled. * The Debug Data pin (DDA) is physically located on either the XTAL1/P3.2 or XTAL2/P3.3 pin. The crystal oscillator is therefore not supported during debug. The user must select either the Internal RC Oscillator or the External Clock source to provide the system clock. Devices fused for the crystal oscillator will default to external clock mode when OCD is enabled. * When using the Internal RC Oscillator during debug, DDA is located on the XTAL1/P3.2 pin. The INT0 function cannot be emulated in this mode. * When using the External Clock during debug, DDA is located on the XTAL2/P3.3 pin and the system clock drives XTAL1/P3.2. The INT0, INT1 and CLKOUT functions cannot be emulated in this mode. * The AT89LP213/214 does not support In-Application Programming and therefore the device must be reset before changing the program code during debugging. This includes the insertion/deletion of software breakpoints. * When using the watchdog to generate a break, the state of the watchdog will not be reset. An OCD reset command should be sent to the device prior to resuming normal execution to ensure correct watchdog behavior. 64 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 23. Programming the Flash Memory The Atmel AT89LP213/214 microcontroller features 2KB of on-chip In-System Programmable Flash program memory. In-System Programming (ISP) allows programming and reprogramming of the microcontroller positioned inside the end system. Using a simple 4-wire SPI interface, the In-System programmer communicates serially with the AT89LP213/214 microcontroller, reprogramming all nonvolatile memories on the chip. In-System programming eliminates the need for physical removal of the chips from the system. This will save time and money, both during development in the lab, and when updating the software or parameters in the field. The ISP interface of the AT89LP213/214 includes the following features: * Four Wire SPI Programming Interface * Active-low Reset Entry into Programming * Slave Select allows multiple devices on same interface * User Signature Array * Flexible Page Programming * Row Erase Capability * Page Write with Auto-Erase Commands * Programming Status Register For more detailed information on In-System Programming, refer to the Application Note entitled "AT89LP In-System Programming Specification". 23.1 Physical Interface In-System Programming utilizes the Serial Peripheral Interface (SPI) pins of an AT89LP213/214 microcontroller. The SPI is a full duplex synchronous serial interface consisting of four wires: Serial Clock (SCK), Master-In/Slave-out (MISO), Master-out/Slave-in (MOSI), and an active-low Slave Select (SS). When programming an AT89LP213/214 device, the programmer always operates as the SPI master, and the target system always operates as the SPI slave. To enter or remain in In-System Programming mode the device's reset line (RST) must be held active (low). With the addition of VCC and GND, an AT89LP213/214 microcontroller can be programmed with a minimum of seven connections as shown in Figure 23-1. Figure 23-1. In-System Programming Device Connections AT89LP213/214 Serial Clock Serial Out Serial In SS P1.7/SCK P1.6/MISO P1.5/MOSI P1.4/SS P1.3/RST GND RST VCC 65 3538A-MICRO-7/06 The In-System Programming Interface is the only means of externally programming the AT89LP213/214 microcontroller. The ISP Interface can be used to program the device both insystem and in a stand-alone serial programmer. The ISP Interface does not require any clock other than SCK and is not limited by the system clock frequency. During In-System programming the system clock source of the target device can operate normally. When designing a system where In-System Programming will be used, the following observations must be considered for correct operation: * The ISP interface uses the SPI clock mode 0 (CPOL = 0,CPHA = 0) exclusively with a maximum frequency of 5 MHz. * The AT89LP213/214 will enter programming mode only when its reset line (RST) is active (low). To simplify this operation, it is recommended that the target reset can be controlled by the In-System programmer. To avoid problems, the In-System programmer should be able to keep the entire target system reset for the duration of the programming cycle. The target system should never attempt to drive the four SPI lines while reset is active. * The RST input may be disabled to gain an extra I/O pin. In these cases the RST pin will always function as a reset during power up. To enter programming the RST pin must be driven low prior to the end of Power-On Reset (POR). After POR has completed the device will remain in ISP mode until RST is brought high. Once the initial ISP session has ended, the power to the target device must be cycled OFF and ON to enter another session. * The SS pin should not be left floating during reset if ISP is enabled. * The ISP Enable Fuse must be set to allow programming during any reset period. If the ISP Fuse is disabled, ISP may only be entered at POR. 23.2 Memory Organization The AT89LP213/214 offers 2K bytes of In-System Programmable (ISP) nonvolatile Flash code memory. In addition, the device contains a 64-byte User Signature Array and a 32-byte readonly Atmel Signature Array. The memory organization is shown in Table 23-1 and Figure 23-2. The memory is divided into pages of 32 bytes each. A single read or write command may only access a single page in the memory. Each memory type resides in its own address space and is accessed by commands specific to that memory. However, all memory types share the same page size. User configuration fuses are mapped as a row in the memory, with each byte representing one fuse. From a programming standpoint, fuses are treated the same as normal code bytes except they are not affected by Chip Erase. Fuses can be enabled at any time by writing 00h to the appropriate locations in the fuse row. However, to disable a fuse, i.e. set it to FFh, the entire fuse row must be erased and then reprogrammed. The programmer should read the state of all the fuses into a temporary location, modify those fuses which need to be disabled, then issue a Fuse Write with Auto-Erase command using the temporary data. Lock bits are treated in a similar manner to fuses except they may only be erased (unlocked) by Chip Erase. Table 23-1. Device # AT89LP213 AT89LP214 Code Memory Sizes Code Size 2K bytes 2K bytes Page Size 32 bytes 32 bytes # Pages 64 64 Address Range 0000H - 07FFH 0000H - 07FFH 66 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] Figure 23-2. AT89LP213/214 Memory Organization User Fuse Row User Signature Array Atmel Signature Array Page 0 Page 1 Page 0 Page 0 Page 63 Page 62 07FF Code Memory Page 1 Page 0 00 1F 0000 23.3 Command Format Programming commands consist of an opcode byte, two address bytes, and zero or more data bytes. In addition, all command packets must start with a two-byte preamble of AAH and 55H. The preamble increases the noise immunity of the programming interface by making it more difficult to issue unintentional commands. Figure 23-3 on page 68 shows a simplified flow chart of a command sequence. A sample command packet is shown in Figure 23-4 on page 68. The SS pin defines the packet frame. SS must be brought low before the first byte in a command is sent and brought back high after the final byte in the command has been sent. The command is not complete until SS returns high. Command bytes are issued serially on MOSI. Data output bytes are received serially on MISO. Packets of variable length are supported by returning SS high when the final required byte has been transmitted. In some cases command bytes have a don't care value. Don't care bytes in the middle of a packet must be transmitted. Don't care bytes at the end of a packet may be ignored. Page oriented instructions always include a full 16-bit address. The higher order bits select the page and the lower order bits select the byte within that page. The AT89LP213/214 allocates 5 bits for byte address and 6 bits for page address. The page to be accessed is always fixed by the page address as transmitted. The byte address specifies the starting address for the first data byte. After each data byte has been transmitted, the byte address is incremented to point to the next data byte. This allows a page command to linearly sweep the bytes within a page. If the byte address is incremented past the last byte in the page, the byte address will roll over to the first byte in the same page. While loading bytes into the page buffer, overwriting previously loaded bytes will result in data corruption. For a summary of available commands, see Table 23-2 on page 69. 67 3538A-MICRO-7/06 Figure 23-3. Command Sequence Flow Chart Input Preamble 1 (AAh) Input Preamble 2 (55h) Input Opcode Input Address High Byte Input Address Low Byte Input/Output Data Address +1 Figure 23-4. ISP Command Packet SS SCK MOSI Preamble 1 Preamble 2 X 76543210 Opcode X 76543210 Address High X 76543210 Address Low X 76543210 Data In 76543210 Data Out MISO X 68 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] Table 23-2. Command Program Enable(1) Chip Erase Read Status Load Page Buffer(2) Write Code Page(2) Write Code Page with Auto-Erase(2) Read Code Page(2) Write User Fuses(2)(3)(4) Write User Fuses with Auto-Erase(2)(3)(4) Read User Fuses(2)(3)(4) Write Lock Bits(2)(3)(5) Read Lock Bits(2)(3)(5) Write User Signature Page(2) Write User Signature Page with Auto-Erase(2) Read User Signature Page(2) Read Atmel Signature Page(2)(6) Notes: Programming Command Summary Opcode 1010 1100 1000 1010 0110 0000 0101 0001 0101 0000 0111 0000 0011 0000 1110 0001 1111 0001 0110 0001 1110 0100 0110 0100 0101 0010 0111 0010 0011 0010 0011 1000 Addr High 0101 0011 - xxxx xxxx xxxx xxxx xxxx xaaa xxxx xaaa xxxx xaaa 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Addr Low - - xxxx xxxx xxxb bbbb aaab bbbb aaab bbbb aaab bbbb 000b bbbb 000b bbbb 000b bbbb 000b bbbb 000b bbbb xaab bbbb xaab bbbb xaab bbbb xxxb bbbb Data 0 - - Status Out DataIn 0 ... DataIn n DataIn 0 ... DataIn n DataIn 0 ... DataIn n DataOut 0 ... DataOut n DataIn 0 ... DataIn n DataIn 0 ... DataIn n DataOut 0 ... DataOut n DataIn 0 ... DataIn n DataOut 0 ... DataOut n DataIn 0 ... DataIn n DataIn 0 ... DataIn n DataOut 0 ... DataOut n DataOut 0 ... DataOut n Data n - - 1. Program Enable must be the first command issued after entering into programming mode. 2. Any number of Data bytes from 1 to 32 may be written/read. The internal address is incremented between each byte. 3. Each byte address selects one fuse or lock bit. Data bytes must be 00h or FFh. 4. See Table 23-5 on page 71 for Fuse definitions. 5. See Table 23-4 on page 70 for Lock Bit definitions. 6. Atmel Signature Bytes: AT89LP213: Address 00H = 1EH 01H = 27H 02H = FFH AT89LP214: Address 00H = 1EH 01H = 28H 02H = FFH 7. Symbol Key: a: b: x: Page Address Bit Byte Address Bit Don't Care Bit 69 3538A-MICRO-7/06 23.4 Status Register The current state of the memory may be accessed by reading the status register. The status register is shown in Table 23-3. Table 23-3. Status Register - Bit Symbol LOAD SUCCESS 7 Function - 6 - 5 - 4 LOAD 3 SUCCESS 2 WRTINH 1 BUSY 0 Load flag. Cleared low by the load page buffer command and set high by the next memory write. This flag signals that the page buffer was previously loaded with data by the load page buffer command. Success flag. Cleared low at the start of a programming cycle and will only be set high if the programming cycle completes without interruption from the brownout detector. Write Inhibit flag. Cleared low by the brownout detector (BOD) whenever programming is inhibited due to VCC falling below the minimum required programming voltage. If a BOD episode occurs during programming, the SUCCESS flag will remain low after the cycle is complete. WRTINH low also forces BUSY low. Busy flag. Cleared low whenever the memory is busy programming or if write is currently inhibited. WRTINH BUSY 23.5 DATA Polling The AT89LP213/214 implements DATA polling to indicate the end of a programming cycle. While the device is busy, any attempted read of the last byte written will return the data byte with the MSB complemented. Once the programming cycle has completed, the true value will be accessible. During Erase the data is assumed to be FFH and DATA polling will return 7FH. When writing multiple bytes in a page, the DATA value will be the last data byte loaded before programming begins, not the written byte with the highest physical address within the page. 23.6 Flash Security The AT89LP213/214 provides two Lock Bits for Flash Code Memory security. Lock bits can be left unprogrammed (FFh) or programmed (00h) to obtain the protection levels listed in Table 234. Lock bits can only be erased (set to FFh) by Chip Erase. Lock bit mode 2 disables programming of all memory spaces, including the User Signature Array and User Configuration Fuses. User fuses must be programmed before enabling Lock bit mode 2 or 3. Lock bit mode 3 implemented mode 2 and also blocks reads from the code memory; however, reads of the User Signature Array, Atmel Signature Array, and User Configuration Fuses are still allowed. Table 23-4. Lock Bit Protection Modes Program Lock Bits (by address) Mode 1 2 3 00h FFh 00h 00h 01h FFh FFh 00h Protection Mode No program lock features Further programming of the Flash is disabled Further programming of the Flash is disabled and verify (read) is also disabled; OCD is disabled 70 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 23.7 User Configuration Fuses The AT89LP213/214 includes 19 user fuses for configuration of the device. Each fuse is accessed at a separate address in the User Fuse Row as listed in Table 23-5. Fuses are cleared by programming 00h to their locations. Programming FFh to fuse location will cause that fuse to maintain its previous state. To set a fuse (set to FFh) the fuse row must be erased and then reprogrammed using the Fuse Write with Auto-erase command. The default state for all fuses is FFh. Table 23-5. Address User Configuration Fuse Definitions Fuse Name Description Selects source for the system clock: CS1 CS0 00h FFh 00h FFh Selected Source Crystal Oscillator (XTAL) Reserved External Clock on XTAL1 (XCLK) Internal RC Oscillator (IRC) 00 - 01h Clock Source - CS[0:1](2) 00h 00h FFh FFh Selects time-out delay for the POR/BOD/PWD wake-up period: SUT1 Start-up Time - SUT[0:1] 02 - 03h 00h FFh FFh 04h 05h 06h 07h 08 - 0FH 10H 11H 12H Notes: Reset Pin Enable(3) Brown-out Detector Enable On-chip Debug Enable ISP Enable(3) RC Oscillator Frequency Adjustment [0:7] User Signature Programming Tristate Ports OCD Interface Select 1. The default state for all fuses is FFh. 2. Changes to these fuses will only take effect after a device POR. 3. Changes to these fuses will only take effect after the ISP session terminates by bringing RST high. FFh 00h FFh 2 ms (XTAL); 512 s (XCLK/IRC) 4 ms (XTAL); 1 ms (XCLK/IRC) 16 ms (XTAL); 4 ms (XCLK/IRC) 00h SUT0 00h Selected Time-out 1 ms (XTAL); 16 s (XCLK/IRC) FFh: RST pin functions as reset 00h: RST pin functions as general purpose I/O FFh: Brown-out Detector Enabled 00h: Brown-out Detector Disabled FFh: On-chip Debug Disabled 00h: On-chip Debug Enabled FFh: In-System Programming Enabled 00h: In-System Programming Disabled (Enabled at POR only) Adjusts the frequency of the internal RC oscillator. FFh: Programming of User Signature Disabled 00h: Programming of User Signature Enabled FFh: I/O Ports start in input-only mode (tristated) after reset 00h: I/O Ports start in quasi-bidirectional mode after reset FFh: Normal two-wire interface 00h: Fast two-wire interface 71 3538A-MICRO-7/06 23.8 Programming Interface Timing This section details general system timing sequences and constraints for entering or exiting InSystem Programming as well as parameters related to the Serial Peripheral Interface during ISP. The general timing parameters for the following waveform figures are listed in Section 23.8.6 "Timing Parameters" on page 75. 23.8.1 Power-up Sequence Execute this sequence to enter programming mode immediately after power-up. In the RST pin is disabled or if the ISP Fuse is disabled, this is the only method to enter programming (see Section 10.3 "External Reset" on page 15). 1. Apply power between VCC and GND pins. RST should remain low. 2. Wait at least tPWRUP. and drive SS high. 3. Wait at least tSUT for the internal Power-on Reset to complete. The value of tSUT will depend on the current settings of the device. 4. Start programming session. Figure 23-5. Serial Programming Power-up Sequence VCC RST SS SCK MISO MOSI HIGH Z HIGH Z tPOR + tSUT tZSS tPWRUP 23.8.2 Power-down Sequence Execute this sequence to power-down the device after programming. 1. Drive SCK low. 2. Wait at least tSSD and bring SS high. 3. Tristate MOSI. 4. Wait at least tSSZ and then tristate SS and SCK. 5. Wait no more than tPWRDN and power off VCC. Figure 23-6. Serial Programming Power-down Sequence VCC RST SS SCK MISO MOSI tSSD tSSZ HIGH Z HIGH Z tPWRDN 72 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 23.8.3 ISP Start Sequence Execute this sequence to exit CPU execution mode and enter ISP mode when the device has passed Power-on Reset and is already operational. 1. Drive RST low. 2. Drive SS high. 3. Wait tRLZ + tSTL. 4. Start programming session. Figure 23-7. In-System Programming (ISP) Start Sequence VCC XTAL1 RST SS SCK MISO MOSI HIGH Z HIGH Z tSTL tZSS tSSE tRLZ 23.8.4 ISP Exit Sequence Execute this sequence to exit ISP mode and resume CPU execution mode. 1. Drive SCK low. 1. Wait at least tSSD and drive SS high. 2. Tristate MOSI. 3. Wait at least tSSZ and bring RST high. 4. Tristate SCK. 5. Wait tRHZ and tristate SS. Figure 23-8. In-System Programming (ISP) Exit Sequence VCC XTAL1 RST SS SCK MISO MOSI tSSD HIGH Z HIGH Z tSSZ tRHZ Note: The waveforms on this page are not to scale. 73 3538A-MICRO-7/06 23.8.5 Serial Peripheral Interface The Serial Peripheral Interface (SPI) is a byte-oriented full duplex synchronous serial communication channel. During In-System programming the programmer always acts as the SPI master and the target device always acts as the SPI slave. The target device receives serial data on MOSI and outputs serial data on MISO. The Programming Interface implements a standard SPI Port with a fixed data order and For In-System programming, bytes are transferred MSB first as shown in Figure 23-9. The SCK phase and polarity follow SPI clock mode 0 (CPOL = 0, CPHA = 0) where bits are sampled on the rising edge of SCK and output on the falling edge of SCK. For more detailed timing information see Figure 23-10. Figure 23-9. ISP Byte Sequence SCK MOSI MISO 7 7 6 6 5 5 Data Sampled 4 4 3 3 2 2 1 1 0 0 Figure 23-10. Serial Programming Interface Timing SS tSSE tSCK tSHSL tSOE tSR tSLSH tSOV tSOH tSIS tSIH tSOX tSF tSSD SCK MISO MOSI 74 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 23.8.6 Timing Parameters The timing parameters for Figure 23-5, Figure 23-6, Figure 23-7, Figure 23-8, and Figure 23-10 are shown in Table 23-6. Table 23-6. Symbol tCLCL tPWRUP tPOR tPWRDN tRLZ tSTL tRHZ tSCK tSHSL tSLSH tSR tSF tSIS tSIH tSOH tSOV tSOE tSOX tSSE tSSD tZSS tSSZ tWR tAWR tERS Note: Programming Interface Timing Parameters Parameter System Clock Cycle Time Power On to SS High Time Power-on Reset Time SS Tristate to Power Off RST Low to I/O Tristate RST Low Settling Time RST High to SS Tristate Serial Clock Cycle Time Clock High Time Clock Low Time Rise Time Fall Time Serial Input Setup Time Serial Input Hold Time Serial Output Hold Time Serial Output Valid Time Output Enable Time Output Disable Time SS Enable Lead Time SS Disable Lag Time SCK Setup to SS Low SCK Hold after SS High Write Cycle Time Write Cycle with Auto-Erase Time Chip Erase Cycle Time tSLSH tSLSH 25 25 2.5 5 7.5 10 10 10 35 10 25 tCLCL 100 0 200(1) 75 50 25 25 2 tCLCL Min 0 10 100 1 2 tCLCL Max 60 Units ns s s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms 1. tSCK is independent of tCLCL. 75 3538A-MICRO-7/06 24. Electrical Characteristics 24.1 Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Operating Temperature ................................... -40C to +85C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground......-0.7V to +5.5V Maximum Operating Voltage ............................................ 5.5V DC Output Current...................................................... 15.0 mA 24.2 DC Characteristics Parameter Input Low-voltage Input High-voltage Output Low-voltage (1) TA = -40C to 85C, VCC = 2.4V to 5.5V (unless otherwise noted) Symbol VIL VIH VOL Condition Min -0.5 0.2 VCC + 0.9 (Ports 1, 3) IOL = 10 mA, VCC = 2.7V, TA = 85C IOH = -80 A, VCC = 5V 10% VOH Output High-voltage (Ports 1, 3) With Weak Pull-ups Enabled Output High-voltage (Ports 1, 3) With Strong Pull-ups Enabled Logic 0 Input Current (Ports 1, 3) Logic 1 to 0 Transition Current (Ports 1, 3) Input Leakage Current (Port P1.0, P1.1) Comparator Input Offset Voltage Comparator Input Common Mode Voltage Reset Pull-down Resistor Pin Capacitance Test Freq. = 1 MHz, TA = 25C Active Mode, 12 MHz, VCC = 5.5V/3V Power Supply Current ICC Power-down Mode(2) Notes: Idle Mode, 12 MHz, VCC = 5.5V/3V P1.0 & P1.1 = 0V or VCC VCC = 5.5V, P1.0 & P1.1 = 0V or VCC VCC = 3V, P1.0 & P1.1 = 0V or VCC IOH = -30 A IOH = -12 A VOH1 IIL ITL ILI VOS VCM RRST CIO IOH = -10 mA, TA = 85C VIN = 0.45V VIN = 2V, VCC = 5V 10% 0 < VIN < VCC VCC = 5V 0 50 2.4 0.75 VCC 0.9 VCC 0.9 VCC -50 -750 10 20 VCC 150 10 5.5/3.5 1.2/1 100 20 A A A mV V K pF mA mA A A Max 0.2 VCC - 0.1 VCC + 0.5 0.5 Units V V V V V V 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum total IOL for all output pins: 15 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power-down is 2V. 76 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 24.3 Serial Peripheral Interface Timing SPI Master Characteristics Parameter Oscillator Period Serial Clock Cycle Time Clock High Time Clock Low Time Rise Time Fall Time Serial Input Setup Time Serial Input Hold Time Serial Output Hold Time Serial Output Valid Time 10 10 10 35 Min 41.6 4tCLCL tSCK/2 - 25 tSCK/2 - 25 25 25 Max Units ns ns ns ns ns ns ns ns ns ns Table 24-1. Symbol tCLCL tSCK tSHSL tSLSH tSR tSF tSIS tSIH tSOH tSOV Table 24-2. Symbol tCLCL tSCK tSHSL tSLSH tSR tSF tSIS tSIH tSOH tSOV tSOE tSOX tSSE tSSD SPI Slave Characteristics Parameter Oscillator Period Serial Clock Cycle Time Clock High Time Clock Low Time Rise Time Fall Time Serial Input Setup Time Serial Input Hold Time Serial Output Hold Time Serial Output Valid Time Output Enable Time Output Disable Time Slave Enable Lead Time Slave Disable Lag Time 10 0 10 10 10 35 10 25 Min 41.6 4tCLCL 1.5 tCLCL - 25 1.5 tCLCL - 25 25 25 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns 77 3538A-MICRO-7/06 Figure 24-1. SPI Master Timing (CPHA = 0) SS tSCK tSR tSLSH tSF SCK (CPOL = 0) SCK (CPOL = 1) tSHSL tSLSH tSHSL tSIS tSIH MISO tSOH tSOV MOSI Figure 24-2. SPI Slave Timing (CPHA = 0) SS tSSE tSCK tSHSL tSR tSLSH tSF tSSD SCK (CPOL = 0) SCK (CPOL= 1) tSOE tSLSH tSHSL tSOV tSOH tSIS tSIH tSOX MISO MOSI Figure 24-3. SPI Master Timing (CPHA = 1) SS tSCK tSHSL tSLSH tSF tSR SCK (CPOL = 0) SCK (CPOL = 1) MISO MOSI tSLSH tSHSL tSIS tSIH tSOH tSOV 78 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] Figure 24-4. SPI Slave Timing (CPHA = 1) SS tSSE tSCK tSF tSR tSSD SCK (CPOL = 0) SCK (CPOL = 1) tSOE tSHSL tSLSH tSLSH tSHSL tSOV tSOH tSOX MISO tSIS tSIH MOSI 24.4 External Clock Drive Figure 24-5. External Clock Drive Waveform VCC = 2.4V to 5.5V Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall Time Min 0 50 12 12 5 5 Max 20 Units MHz ns ns ns ns ns 79 3538A-MICRO-7/06 24.5 Serial Port Timing: Shift Register Mode Test Conditions Variable Oscillator The values in this table are valid for VCC = 2.4V to 5.5V and Load Capacitance = 80 pF. Symbol tXLXL tQVXH tXHQX tXHDX tXHDV Parameter Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Input Data Hold after Clock Rising Edge Input Data Valid to Clock Rising Edge Min 2tCLCL -15 tCLCL -15 tCLCL -15 0 15 Max Units s ns ns ns ns Figure 24-6. Shift Register Mode Timing Waveform CLOCK WRITE TO SBUF OUTPUT DATA CLEAR RI INPUT DATA VALID VALID VALID VALID VALID VALID VALID VALID 0 1 2 3 4 5 6 7 24.6 24.6.1 Test Conditions AC Testing Input/Output Waveform(1) Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic "1" and 0.45V for a logic "0". Timing measurements are made at VIH min. for a logic "1" and VIL max. for a logic "0". 24.6.2 Float Waveform(1) Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change from the loaded VOH/VOL level occurs. 80 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 24.6.3 ICC Test Condition, Active Mode, All Other Pins are Disconnected VCC ICC RST VCC (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS 24.6.4 ICC Test Condition, Idle Mode, All Other Pins are Disconnected VCC ICC RST VCC (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS 24.6.5 Clock Signal Waveform for ICC Tests in Active and Idle Modes, tCLCH = tCHCL = 5 ns VCC - 0.5V 0.45V 0.7 VCC 0.2 VCC - 0.1V tCHCL tCHCX tCLCL tCHCX tCLCH 24.6.6 ICC Test Condition, Power-down Mode, All Other Pins are Disconnected, VCC = 2V to 5.5V VCC ICC RST VCC (NC) XTAL2 XTAL1 VSS 81 3538A-MICRO-7/06 25. Ordering Information 25.1 Standard Package Power Supply Ordering Code AT89LP213-20PI AT89LP213-20XI 20 2.4V to 5.5V AT89LP214-20PI AT89LP214-20XI 14P3 14X Package 14P3 14X Operation Range Speed (MHz) Industrial (-40 C to 85 C) 25.2 Green Package Option (Pb/Halide-free) Power Supply Ordering Code AT89LP213-20PU AT89LP213-20XU Package 14P3 14X 14P3 14X Operation Range Speed (MHz) 20 2.4V to 5.5V AT89LP214-20PU AT89LP214-20XU Industrial (-40 C to 85 C) Package Type 14P3 14X 14-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 14-lead, 0.173" Wide, Plastic Thin Shrink Small Outline Package (TSSOP) 82 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 26. Packaging Information 26.1 14P3 - PDIP D PIN 1 E1 A SEATING PLANE L B1 e E B A1 C eC eB SYMBOL A A1 D E E1 B Notes: 1. This package conforms to JEDEC reference MS-001, Variation AA. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB eC e COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 18.669 7.620 6.096 0.356 1.143 2.921 0.203 - 0.000 NOM - - - - - - - - - - - MAX 5.334 - 19.685 8.255 7.112 0.559 1.778 3.810 0.356 10.922 1.524 Note 2 Note 2 NOTE 2.540 TYP 11/02/05 2325 Orchard Parkway San Jose, CA 95131 TITLE 14P3, 14-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 14P3 REV. A R 83 3538A-MICRO-7/06 26.2 14X - TSSOP Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. JEDEC Standard MO-153 AB-1. INDEX MARK PIN 1 4.50 (0.177) 6.50 (0.256) 4.30 (0.169) 6.25 (0.246) 5.10 (0.201) 4.90 (0.193) 1.20 (0.047) MAX 0.65 (.0256) BSC 0.30 (0.012) 0.19 (0.007) 0.15 (0.006) 0.05 (0.002) SEATING PLANE 0~ 8 0.20 (0.008) 0.09 (0.004) 0.75 (0.030) 0.45 (0.018) 05/16/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 14X (Formerly "14T"), 14-lead (4.4 mm Body) Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 14X REV. B R 84 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] 27. Revision History Revision No. Revision A - July 2006 History * Initial Release 85 3538A-MICRO-7/06 86 AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] Table of Contents 1. 2. Description ............................................................................................... 1 Pin Configuration ..................................................................................... 2 2.1 2.2 AT89LP213: 14-lead TSSOP/PDIP ......................................................................2 AT89LP214: 14-lead TSSOP/PDIP ......................................................................2 3. 4. 5. Pin Description ......................................................................................... 3 Block Diagram .......................................................................................... 5 Comparison to Standard 8051 ................................................................ 6 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 System Clock .......................................................................................................6 Instruction Execution7/06 with Single-Cycle Fetch ..............................................6 Interrupt Handling .................................................................................................6 Timer/Counters ....................................................................................................6 Serial Port ............................................................................................................6 Watchdog Timer ...................................................................................................7 I/O Ports ...............................................................................................................7 Reset ....................................................................................................................7 6. Memory Organization .............................................................................. 7 6.1 6.2 Program Memory .................................................................................................7 Data Memory ........................................................................................................8 7. 8. 9. Special Function Registers ..................................................................... 9 Enhanced CPU ....................................................................................... 10 8.1 Restrictions on Certain Instructions ...................................................................11 System Clock ......................................................................................... 12 9.1 9.2 9.3 9.4 Crystal Oscillator ................................................................................................12 External Clock Source ........................................................................................12 Internal RC Oscillator .........................................................................................12 System Clock Out ..............................................................................................12 10. Reset ....................................................................................................... 13 10.1 Power-on Reset .................................................................................................13 10.2 Brown-out Reset ................................................................................................15 10.3 External Reset ....................................................................................................15 10.4 Watchdog Reset .................................................................................................16 10.5 Software Reset ...................................................................................................16 i 3538A-MICRO-7/06 Table of Contents (Continued) 11. Power Saving Modes ............................................................................. 16 11.1 Idle Mode ...........................................................................................................16 11.2 Power-down Mode .............................................................................................16 12. Interrupts ................................................................................................ 18 12.1 Interrupt Response Time ....................................................................................20 13. I/O Ports .................................................................................................. 22 13.1 Port Configuration ..............................................................................................22 13.2 Port 1 Analog Functions .....................................................................................25 13.3 Port Read-Modify-Write ......................................................................................25 13.4 Port Alternate Functions .....................................................................................26 14. Enhanced Timer/Counters .................................................................... 27 14.1 Mode 0 - Variable Width Timer/Counter ............................................................27 14.2 Mode 1 - 16-bit Auto-Reload Timer/Counter .....................................................28 14.3 Mode 2 - 8-bit Auto-Reload Timer/Counter .......................................................29 14.4 Mode 3 - 8-bit Split Timer ..................................................................................29 14.5 Pulse Width Modulation .....................................................................................32 15. External Interrupts ................................................................................. 36 16. General-purpose Interrupts .................................................................. 36 17. Serial Interface ....................................................................................... 38 17.1 Multiprocessor Communications ........................................................................38 17.2 Baud Rates ........................................................................................................40 17.3 More About Mode 0 ............................................................................................41 17.4 More About Mode 1 ............................................................................................43 17.5 More About Modes 2 and 3 ................................................................................45 17.6 Framing Error Detection .....................................................................................48 17.7 Automatic Address Recognition .........................................................................48 18. Serial Peripheral Interface ..................................................................... 49 19. Analog Comparator ............................................................................... 55 19.1 Comparator Interrupt with Debouncing ..............................................................55 20. Programmable Watchdog Timer ........................................................... 57 20.1 Software Reset ...................................................................................................58 21. Instruction Set Summary ...................................................................... 59 ii AT89LP213/214 [Preliminary] 3538A-MICRO-7/06 AT89LP213/214 [Preliminary] Table of Contents (Continued) 22. On-Chip Debug System ......................................................................... 63 22.1 Physical Interface ...............................................................................................63 22.2 Software Breakpoints .........................................................................................64 22.3 Limitations of On-Chip Debug ............................................................................64 23. Programming the Flash Memory .......................................................... 65 23.1 Physical Interface ...............................................................................................65 23.2 Memory Organization .........................................................................................66 23.3 Command Format ..............................................................................................67 23.4 Status Register ...................................................................................................70 23.5 DATA Polling ......................................................................................................70 23.6 Flash Security ....................................................................................................70 23.7 User Configuration Fuses ..................................................................................71 23.8 Programming Interface Timing ...........................................................................72 24. Electrical Characteristics ...................................................................... 76 24.1 Absolute Maximum Ratings* ..............................................................................76 24.2 DC Characteristics .............................................................................................76 24.3 Serial Peripheral Interface Timing .....................................................................77 24.4 External Clock Drive ...........................................................................................79 24.5 Serial Port Timing: Shift Register Mode Test Conditions ...................................80 24.6 Test Conditions ..................................................................................................80 25. Ordering Information ............................................................................. 82 25.1 Standard Package ..............................................................................................82 25.2 Green Package Option (Pb/Halide-free) ............................................................82 26. Packaging Information .......................................................................... 83 26.1 14P3 - PDIP ......................................................................................................83 26.2 14X - TSSOP .....................................................................................................84 27. Revision History ..................................................................................... 85 iii 3538A-MICRO-7/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High-Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2006 Atmel Corporation. All rights reserved. Atmel(R), logo and combinations thereof, Everywhere You Are (R) and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 3538A-MICRO-7/06 |
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